/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. * * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * * The SB600 power-on default is to map 256K ROM space. * * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. */ static void sb600_enable_rom(void) { u8 reg8; pci_devfn_t dev; dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB600_LPC), 0); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* * Enable LPC ROM range start at: * 0xfff8(0000): 512KB * 0xfff0(0000): 1MB * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* 4 MB */ /* Enable LPC ROM range end at 0xffff(ffff). */ pci_io_write_config16(dev, 0x6e, 0xffff); }
/* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. * * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * * The HUDSON power-on default is to map 512K ROM space. * */ static void hudson_enable_rom(void) { u8 reg8; pci_devfn_t dev; dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* * Enable LPC ROM range start at: * 0xfff8(0000): 512KB * 0xfff0(0000): 1MB * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ pci_io_write_config16(dev, 0x6e, 0xffff); }
static void sb900_enable_rom(void) { u32 word; u32 dword; device_t dev; dev = PCI_DEV(0, 0x14, 0x03); /* SB900 LPC Bridge 0:20:3:44h. * BIT6: Port Enable for serial port 0x3f8-0x3ff * BIT29: Port Enable for KBC port 0x60 and 0x64 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 */ dword = pci_io_read_config32(dev, 0x44); //dword |= (1<<6) | (1<<29) | (1<<30) ; /*Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword); /* SB900 LPC Bridge 0:20:3:48h. * BIT0: Port Enable for SuperIO 0x2E-0x2F * BIT1: Port Enable for SuperIO 0x4E-0x4F * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) * BIT6: Port Enable for RTC IO 0x70-0x73 * BIT21: Port Enable for Port 0x80 */ dword = pci_io_read_config32(dev, 0x48); dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; pci_io_write_config32(dev, 0x48, dword); /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ /* Set the 4MB enable bits */ word = pci_io_read_config16(dev, 0x6c); word = 0xFFC0; pci_io_write_config16(dev, 0x6c, word); }