int __init pci_visws_init(void) { if (!is_visws_box()) return -1; pcibios_enable_irq = &pci_visws_enable_irq; pcibios_disable_irq = &pci_visws_disable_irq; /* The VISWS supports configuration access type 1 only */ pci_probe = (pci_probe | PCI_PROBE_CONF1) & ~(PCI_PROBE_BIOS | PCI_PROBE_CONF2); pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff; pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff; printk(KERN_INFO "PCI: Lithium bridge A bus: %u, " "bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0); raw_pci_ops = &pci_direct_conf1; pci_scan_bus_with_sysdata(pci_bus0); pci_scan_bus_with_sysdata(pci_bus1); pci_fixup_irqs(visws_swizzle, visws_map_irq); pcibios_resource_survey(); return 0; }
static void __init pirq_peer_trick(void) { struct irq_routing_table *rt = pirq_table; u8 busmap[256]; int i; struct irq_info *e; memset(busmap, 0, sizeof(busmap)); for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { e = &rt->slots[i]; #ifdef DEBUG { int j; DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); for(j=0; j<4; j++) DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); DBG("\n"); } #endif busmap[e->bus] = 1; } for(i = 1; i < 256; i++) { if (!busmap[i] || pci_find_bus(0, i)) continue; if (pci_scan_bus_with_sysdata(i)) printk(KERN_INFO "PCI: Discovered primary peer " "bus %02x [IRQ]\n", i); } pcibios_last_bus = -1; }