void init_lcd()
{
pci_sync_cache(0, (vm_offset_t)__SD_LCD_BAR_BASE, sizeof(__SD_LCD_BAR_BASE), SYNC_R);
memset(SD_LCD_BAR_BASE, 0x00, sizeof(__SD_LCD_BAR_BASE));
init_lcd_regs();
}
int dc_init()
{
int MEM_ADDR =0;
int print_count;
int i;
int PIXEL_COUNT = DIS_WIDTH * DIS_HEIGHT + EXTRA_PIXEL;
int MEM_SIZE = PIXEL_COUNT * 4;
int init_R = 0;
int init_G = 0;
int init_B = 0;
int j,k,l,va,va_mod;
int MEM_SIZE_6 = MEM_SIZE /6;
char *p="AAAAA\nBBBBBBB\nCCCCCCC\nDDDDDDD\nEEEEEEEEEEEEE\nFFFFFFFFFFFFFF\n";
char *q = "";
char convert[3] = {0};
char temp[3] = {0};
//debug for dc malloc
// char *MEM_ptr =(volatile u8*)(MEM_ADDR);
int print_addr;
int print_data;
//////////////////////////////////////////////////////////////
// char *MEM_ptr = (char *)malloc(MEM_SIZE,M_MBUF, 0x1);
char *MEM_ptr = (char *)malloc(MEM_SIZE);
MEM_ADDR = MEM_ptr;
///////////////////////////////////////////////////////////////
printf("enter dc_init...\n");
if(MEM_ptr == NULL)
{
printf("frame buffer memory malloc failed!\n ");
exit(0);
}
else
{
for (i=0;i<MEM_SIZE;i+=4)
{
//paint ARGB 0 255 0 0 high <- low
*(MEM_ptr+i) = 0 ;
*(MEM_ptr+i+1) = 0 ;
*(MEM_ptr+i+2) = 255 ;
*(MEM_ptr+i+3) = 23 ;
}
#ifdef __mips__
printf("==sync cache\n");
pci_sync_cache(0, (vm_offset_t)MEM_ptr, MEM_SIZE, SYNC_W);
#endif
}
printf("frame buffer addr: %x \n",(MEM_ADDR+0x00));
//write_reg(0x501030,0x23456789);
//int *ptr = (int *)malloc(sizeof(int));
//*ptr = (int *)0x501030;
////ptr = 0x501030;
//*ptr = 0x23456789;
//printf("addr:%x data:%x",ptr,(*ptr));
printf("frame buffer data: %x \n",readl((MEM_ADDR+0x00)));
//config display controller panel 0 reg
write_reg((DC_BASE_ADDR+0x00),0x00000000);
write_reg((DC_BASE_ADDR+0x00),0x00000004);
write_reg((DC_BASE_ADDR+0x20),MEM_ADDR );
write_reg((DC_BASE_ADDR+0x40),0x00000500);
write_reg((0xbc301360 +0x00),0x00000000);
write_reg((0xbc301360 +0x20),0x00000000);
write_reg((0xbc301360 +0x40),0x00000000);
write_reg((0xbc301360 +0x60),0x80001111);
write_reg((0xbc301360 +0x80),0x33333333);
write_reg((0xbc301400 +0x00),0x014f0140);
write_reg((0xbc301400 +0x20),0x414a0145);
write_reg((0xbc301400 +0x80),0x00fa00f0);
write_reg((0xbc301400 +0xa0),0x40f700f5);
write_reg((0xbc301520 +0x00),0x00020202);
write_reg((0xbc301530 +0x00),MEM_ADDR );
write_reg((0xbc301540 +0x00),0x00060122);
write_reg((0xbc301550 +0x00),0x00eeeeee);
write_reg((0xbc301560 +0x00),0x00aaaaaa);
//config display controller panel 1 reg
write_reg((DC_BASE_ADDR_1+0x00),0x00000000);
write_reg((DC_BASE_ADDR_1+0x00),0x00000004);
write_reg((DC_BASE_ADDR_1+0x20),MEM_ADDR );
//800x600@60
//write_reg((DC_BASE_ADDR_1+0x40),0x00000C80);
write_reg((DC_BASE_ADDR_1+0x40),0x00000A00); //640
// write_reg((DC_BASE_ADDR_1+0x40),0x00001558); //1366
write_reg((0xbc301370 +0x00),0x00000000);
write_reg((0xbc301370 +0x20),0x00000000);
write_reg((0xbc301370 +0x40),0x00000000);
write_reg((0xbc301370 +0x60),0x80001111);
write_reg((0xbc301370 +0x80),0x33333333);
//write_reg((0xbc301410 +0x00),0x038a0320);
//write_reg((0xbc301410 +0x20),0x43610324);
//write_reg((0xbc301410 +0x80),0x02940240);
//write_reg((0xbc301410 +0xa0),0x426c0264);
//800x600@60
// write_reg((0xbc301410 +0x00),0x04000320);
// write_reg((0xbc301410 +0x20),0x43900340);
// write_reg((0xbc301410 +0x80),0x026E0258);
// write_reg((0xbc301410 +0xa0),0x425C0259);
/*704x598
write_reg((0xbc301410 +0x00),0x038002C0);
write_reg((0xbc301410 +0x20),0x432002D8);
write_reg((0xbc301410 +0x80),0x026B0256);
write_reg((0xbc301410 +0xa0),0x425A0257);
*/
// 640x480@60 frequecy:23.86hz
// write_reg((0xbc301410 +0x00),0x03200280);
// write_reg((0xbc301410 +0x20),0x42D00290);
// write_reg((0xbc301410 +0x80),0x01F101E0);
// write_reg((0xbc301410 +0xa0),0x41E401E1);
// 640x480@60 frequecy:25.18hz
write_reg((0xbc301410 +0x00),0x03200280);
write_reg((0xbc301410 +0x20),0x42F00290);
write_reg((0xbc301410 +0x80),0x020D01E0);
write_reg((0xbc301410 +0xa0),0x41EC01EA);
//1366*768@20 23.78Hz
//write_reg((0xbc301410 +0x00),0x07080556);
//write_reg((0xbc301410 +0x20),0x463005A0);
//write_reg((0xbc301410 +0x80),0x031B0300);
//write_reg((0xbc301410 +0xa0),0x43040301);
// 640x480@60 frequecy:23.86hz another set
//write_reg((0xbc301410 +0x00),0x03200280);
//write_reg((0xbc301410 +0x20),0x42F00290);
//write_reg((0xbc301410 +0x80),0x020D01E0);
//write_reg((0xbc301410 +0xa0),0x41EC01EA);
//640x480@50
// write_reg((0xbc301410 +0x00),0x03100280);
// write_reg((0xbc301410 +0x20),0x42C80288);
// write_reg((0xbc301410 +0x80),0x01EF01E0);
// write_reg((0xbc301410 +0xa0),0x41E401E1);
write_reg((0xbc301520 +0x00),0x00020202);
write_reg((0xbc301530 +0x00),MEM_ADDR );
write_reg((0xbc301540 +0x00),0x00020002);
write_reg((0xbc301550 +0x00),0x00eeeeee);
write_reg((0xbc301560 +0x00),0x00aaaaaa);
write_reg((DC_BASE_ADDR+0x00),0x00100104);
write_reg((DC_BASE_ADDR_1+0x00),0x00100104);
printf("display controller reg config complete!\n");
printf("read reg addr begin...\n");
printf("read panel 0 reg:\n");
print_data = readl((DC_BASE_ADDR+0x00));
printf("read first data successfully!\n");
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR+0x00),print_data);
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR+0x00),(readl((DC_BASE_ADDR+0x00))));
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR+0x20),(readl((DC_BASE_ADDR+0x20))));
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR+0x40),(readl((DC_BASE_ADDR+0x40))));
printf("reg addr:%x,reg data:%x\n",(0xbc301360 +0x00),(readl((0xbc301360 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301360 +0x20),(readl((0xbc301360 +0x20))));
printf("reg addr:%x,reg data:%x\n",(0xbc301360 +0x40),(readl((0xbc301360 +0x40))));
printf("reg addr:%x,reg data:%x\n",(0xbc301360 +0x60),(readl((0xbc301360 +0x60))));
printf("reg addr:%x,reg data:%x\n",(0xbc301360 +0x80),(readl((0xbc301360 +0x80))));
printf("reg addr:%x,reg data:%x\n",(0xbc301400 +0x00),(readl((0xbc301400 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301400 +0x20),(readl((0xbc301400 +0x20))));
printf("reg addr:%x,reg data:%x\n",(0xbc301400 +0x80),(readl((0xbc301400 +0x80))));
printf("reg addr:%x,reg data:%x\n",(0xbc301400 +0xa0),(readl((0xbc301400 +0xa0))));
printf("reg addr:%x,reg data:%x\n",(0xbc301520 +0x00),(readl((0xbc301520 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301530 +0x00),(readl((0xbc301530 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301540 +0x00),(readl((0xbc301540 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301550 +0x00),(readl((0xbc301550 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301560 +0x00),(readl((0xbc301560 +0x00))));
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR+0x00),(readl((DC_BASE_ADDR+0x00))));
printf("\n\nread panel 1 reg:\n");
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR_1+0x00),(readl((DC_BASE_ADDR_1+0x00))));
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR_1+0x20),(readl((DC_BASE_ADDR_1+0x20))));
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR_1+0x40),(readl((DC_BASE_ADDR_1+0x40))));
printf("reg addr:%x,reg data:%x\n",(0xbc301370 +0x00),(readl((0xbc301370 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301370 +0x20),(readl((0xbc301370 +0x20))));
printf("reg addr:%x,reg data:%x\n",(0xbc301370 +0x40),(readl((0xbc301370 +0x40))));
printf("reg addr:%x,reg data:%x\n",(0xbc301370 +0x60),(readl((0xbc301370 +0x60))));
printf("reg addr:%x,reg data:%x\n",(0xbc301370 +0x80),(readl((0xbc301370 +0x80))));
printf("reg addr:%x,reg data:%x\n",(0xbc301410 +0x00),(readl((0xbc301410 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301410 +0x20),(readl((0xbc301410 +0x20))));
printf("reg addr:%x,reg data:%x\n",(0xbc301410 +0x80),(readl((0xbc301410 +0x80))));
printf("reg addr:%x,reg data:%x\n",(0xbc301410 +0xa0),(readl((0xbc301410 +0xa0))));
printf("reg addr:%x,reg data:%x\n",(0xbc301520 +0x00),(readl((0xbc301520 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301530 +0x00),(readl((0xbc301530 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301540 +0x00),(readl((0xbc301540 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301550 +0x00),(readl((0xbc301550 +0x00))));
printf("reg addr:%x,reg data:%x\n",(0xbc301560 +0x00),(readl((0xbc301560 +0x00))));
printf("reg addr:%x,reg data:%x\n",(DC_BASE_ADDR_1+0x00),(readl((DC_BASE_ADDR_1+0x00))));
printf("read frame buffer begin...\n");
for(j=0;j<DIS_HEIGHT;j+=100)
{
// printf("line %d;\n",j);
for (i=1;i<DIS_WIDTH*4;i+=4*10)
{
printf("%x %x %x %x \t",*(MEM_ptr+j*DIS_WIDTH*4+i-1),*(MEM_ptr+j*DIS_WIDTH*4+i),*(MEM_ptr+j*DIS_WIDTH*4+i+1),*(MEM_ptr+j*DIS_WIDTH*4+i+2));
}
// printf("\n\n\n\n");
}
printf("\nGPU twodclearl test begin...\n");
gpu_reg_wr();
gpu_twodclearl(MEM_ptr);
printf("write cmd buff end...\n");
gpu_reg_wr();
//wait
for(j=0;j<500;j++)
{
printf("debug out reg:%x\n",readl(0xbc200004));
}
printf("wait end...\n");
printf("read frame buffer begin...\n");
for(j=0;j<DIS_HEIGHT;j+=100)
{
// printf("line %d;\n",j);
for (i=1;i<DIS_WIDTH*4;i+=4*10)
{
printf("%x %x %x %x \t",*(MEM_ptr+j*DIS_WIDTH*4+i-1),*(MEM_ptr+j*DIS_WIDTH*4+i),*(MEM_ptr+j*DIS_WIDTH*4+i+1),*(MEM_ptr+j*DIS_WIDTH*4+i+2));
}
// printf("\n\n\n\n");
}
#ifdef __mips__
printf("==sync cache\n");
pci_sync_cache(0, (vm_offset_t)MEM_ptr,MEM_SIZE, SYNC_W);
#endif
return 0;
}
