SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn, unsigned long, off, unsigned long, len, void __user *, buf) { struct pci_dev *dev; u8 byte; u16 word; u32 dword; long err; long cfg_ret; if (!capable(CAP_SYS_ADMIN)) return -EPERM; err = -ENODEV; dev = pci_get_bus_and_slot(bus, dfn); if (!dev) goto error; switch (len) { case 1: cfg_ret = pci_user_read_config_byte(dev, off, &byte); break; case 2: cfg_ret = pci_user_read_config_word(dev, off, &word); break; case 4: cfg_ret = pci_user_read_config_dword(dev, off, &dword); break; default: err = -EINVAL; goto error; } err = -EIO; if (cfg_ret != PCIBIOS_SUCCESSFUL) goto error; switch (len) { case 1: err = put_user(byte, (unsigned char __user *)buf); break; case 2: err = put_user(word, (unsigned short __user *)buf); break; case 4: err = put_user(dword, (unsigned int __user *)buf); break; } pci_dev_put(dev); return err; error: /* ??? XFree86 doesn't even check the return value. They just look for 0xffffffff in the output, since that's what they get instead of a machine check on x86. */ switch (len) { case 1: put_user(-1, (unsigned char __user *)buf); break; case 2: put_user(-1, (unsigned short __user *)buf); break; case 4: put_user(-1, (unsigned int __user *)buf); break; } pci_dev_put(dev); return err; }
static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count, void *arg) { struct pci_vpd *vpd = dev->vpd; int ret; loff_t end = pos + count; u8 *buf = arg; if (pos < 0) return -EINVAL; if (!vpd->valid) { vpd->valid = 1; vpd->len = pci_vpd_size(dev, vpd->len); } if (vpd->len == 0) return -EIO; if (pos > vpd->len) return 0; if (end > vpd->len) { end = vpd->len; count = end - pos; } if (mutex_lock_killable(&vpd->lock)) return -EINTR; ret = pci_vpd_wait(dev); if (ret < 0) goto out; while (pos < end) { u32 val; unsigned int i, skip; ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR, pos & ~3); if (ret < 0) break; vpd->busy = 1; vpd->flag = PCI_VPD_ADDR_F; ret = pci_vpd_wait(dev); if (ret < 0) break; ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val); if (ret < 0) break; skip = pos & 3; for (i = 0; i < sizeof(u32); i++) { if (i >= skip) { *buf++ = val; if (++pos == end) break; } val >>= 8; } } out: mutex_unlock(&vpd->lock); return ret ? ret : count; }
static ssize_t proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) { struct pci_dev *dev = PDE_DATA(file_inode(file)); unsigned int pos = *ppos; unsigned int cnt, size; /* * Normal users can read only the standardized portion of the * configuration space as several chips lock up when trying to read * undefined locations (think of Intel PIIX4 as a typical example). */ if (capable(CAP_SYS_ADMIN)) size = dev->cfg_size; else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) size = 128; else size = 64; if (pos >= size) return 0; if (nbytes >= size) nbytes = size; if (pos + nbytes > size) nbytes = size - pos; cnt = nbytes; if (!access_ok(VERIFY_WRITE, buf, cnt)) return -EINVAL; pci_config_pm_runtime_get(dev); if ((pos & 1) && cnt) { unsigned char val; pci_user_read_config_byte(dev, pos, &val); __put_user(val, buf); buf++; pos++; cnt--; } if ((pos & 3) && cnt > 2) { unsigned short val; pci_user_read_config_word(dev, pos, &val); __put_user(cpu_to_le16(val), (__le16 __user *) buf); buf += 2; pos += 2; cnt -= 2; } while (cnt >= 4) { unsigned int val; pci_user_read_config_dword(dev, pos, &val); __put_user(cpu_to_le32(val), (__le32 __user *) buf); buf += 4; pos += 4; cnt -= 4; } if (cnt >= 2) { unsigned short val; pci_user_read_config_word(dev, pos, &val); __put_user(cpu_to_le16(val), (__le16 __user *) buf); buf += 2; pos += 2; cnt -= 2; } if (cnt) { unsigned char val; pci_user_read_config_byte(dev, pos, &val); __put_user(val, buf); buf++; pos++; cnt--; } pci_config_pm_runtime_put(dev); *ppos = pos; return nbytes; }