void intel_sandybridge_finalize_smm(void) { pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ MCHBAR32_OR(0x6800, 1 << 31); MCHBAR32_OR(0x7000, 1 << 31); MCHBAR32_OR(0x77fc, 1 << 0); /* Memory Controller Lockdown */ MCHBAR8(0x50fc) = 0x8f; /* Read+write the following */ MCHBAR32(0x6030) = MCHBAR32(0x6030); MCHBAR32(0x6034) = MCHBAR32(0x6034); MCHBAR32(0x6008) = MCHBAR32(0x6008); }
void intel_pch_finalize_smm(void) { /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; RCBA16(0x3896) = SPI_OPTYPE; RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); #if CONFIG_SPI_FLASH_SMM /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31)); /* BIOS Interface Lockdown */ RCBA32_OR(0x3410, (1 << 0)); /* Function Disable SUS Well Lockdown */ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); }