static uint32_t
pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
{
if (cfgmech == CFGMECH_PCIE &&
(bus >= pcie_minbus && bus <= pcie_maxbus) &&
(bus != 0 || !(1 << slot & pcie_badslots)))
return pciereg_cfgread(bus, slot, func, reg, bytes);
else
return pcireg_cfgread(bus, slot, func, reg, bytes);
}
int
pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
{
if (bootverbose) {
kprintf("PCIe: Memory Mapped configuration base @ 0x%jx, "
"bus [%d, %d]\n", (uintmax_t)base, minbus, maxbus);
}
if (!mcfg_enable)
return 0;
if (minbus != 0)
return 0;
if (bootverbose)
kprintf("PCIe: Using Memory Mapped configuration\n");
pcie_base = (vm_offset_t)pmap_mapdev_uncacheable(base,
((unsigned)maxbus + 1) << 20);
pcie_minbus = minbus;
pcie_maxbus = maxbus;
cfgmech = CFGMECH_PCIE;
/*
* On some AMD systems, some of the devices on bus 0 are
* inaccessible using memory-mapped PCI config access. Walk
* bus 0 looking for such devices. For these devices, we will
* fall back to using type 1 config access instead.
*/
if (pci_cfgregopen() != 0) {
int slot;
for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
uint32_t val1, val2;
val1 = pcireg_cfgread(0, slot, 0, 0, 4);
if (val1 == 0xffffffff)
continue;
val2 = pciereg_cfgread(0, slot, 0, 0, 4);
if (val2 != val1)
pcie_badslots |= (1 << slot);
}
}
return 1;
}
int
pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
{
uint32_t val1, val2;
int slot;
if (!mcfg_enable)
return (0);
if (minbus != 0)
return (0);
if (bootverbose)
printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
base);
/* XXX: We should make sure this really fits into the direct map. */
pcie_base = (vm_offset_t)pmap_mapdev(base, (maxbus + 1) << 20);
pcie_minbus = minbus;
pcie_maxbus = maxbus;
cfgmech = CFGMECH_PCIE;
/*
* On some AMD systems, some of the devices on bus 0 are
* inaccessible using memory-mapped PCI config access. Walk
* bus 0 looking for such devices. For these devices, we will
* fall back to using type 1 config access instead.
*/
if (pci_cfgregopen() != 0) {
for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
val1 = pcireg_cfgread(0, slot, 0, 0, 4);
if (val1 == 0xffffffff)
continue;
val2 = pciereg_cfgread(0, slot, 0, 0, 4);
if (val2 != val1)
pcie_badslots |= (1 << slot);
}
}
return (1);
}
