static void via_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp, pcireg_t interface, int (*pci_intr)(void *)) { struct ata_channel *wdc_cp; struct pciide_softc *sc; prop_bool_t compat_nat_enable; wdc_cp = &cp->ata_channel; sc = CHAN_TO_PCIIDE(&cp->ata_channel); compat_nat_enable = prop_dictionary_get( device_properties(sc->sc_wdcdev.sc_atac.atac_dev), "use-compat-native-irq"); if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) { /* native mode with irq 14/15 requested? */ if (compat_nat_enable != NULL && prop_bool_true(compat_nat_enable)) via_mapregs_compat_native(pa, cp); else pciide_mapregs_native(pa, cp, pci_intr); } else { pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); } wdcattach(wdc_cp); }
static void cy693_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) { struct pciide_channel *cp; pcireg_t interface = PCI_INTERFACE(pa->pa_class); if (pciide_chipen(sc, pa) == 0) return; /* * this chip has 2 PCI IDE functions, one for primary and one for * secondary. So we need to call pciide_mapregs_compat() with * the real channel */ if (pa->pa_function == 1) { sc->sc_cy_compatchan = 0; } else if (pa->pa_function == 2) { sc->sc_cy_compatchan = 1; } else { aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, "unexpected PCI function %d\n", pa->pa_function); return; } if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, "bus-master DMA support present\n"); pciide_mapreg_dma(sc, pa); } else { aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, "hardware does not support DMA\n"); sc->sc_dma_ok = 0; } sc->sc_cy_handle = cy82c693_init(pa->pa_iot); if (sc->sc_cy_handle == NULL) { aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, "unable to map hyperCache control registers\n"); sc->sc_dma_ok = 0; } sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; if (sc->sc_dma_ok) { sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; sc->sc_wdcdev.irqack = pciide_irqack; } sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; sc->sc_wdcdev.sc_atac.atac_set_modes = cy693_setup_channel; sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; sc->sc_wdcdev.sc_atac.atac_nchannels = 1; sc->sc_wdcdev.wdc_maxdrives = 2; wdc_allocate_regs(&sc->sc_wdcdev); /* Only one channel for this chip; if we are here it's enabled */ cp = &sc->pciide_channels[0]; sc->wdc_chanarray[0] = &cp->ata_channel; cp->name = PCIIDE_CHANNEL_NAME(0); cp->ata_channel.ch_channel = 0; cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; cp->ata_channel.ch_queue = malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); if (cp->ata_channel.ch_queue == NULL) { aprint_error("%s primary channel: " "can't allocate memory for command queue", device_xname(sc->sc_wdcdev.sc_atac.atac_dev)); return; } aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, "primary channel %s to ", (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? "configured" : "wired"); if (interface & PCIIDE_INTERFACE_PCI(0)) { aprint_normal("native-PCI mode\n"); pciide_mapregs_native(pa, cp, pciide_pci_intr); } else { aprint_normal("compatibility mode\n"); pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan); if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan); } wdcattach(&cp->ata_channel); }