/** * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure */ static int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; int retries = 1000; int ret; usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) return ret; ret = phy_init(dwc->usb3_generic_phy); if (ret < 0) { phy_exit(dwc->usb2_generic_phy); return ret; } /* * We're resetting only the device side because, if we're in host mode, * XHCI driver will reset the host block. If dwc3 was configured for * host-only mode, then we can return early. */ if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->is_hibernated == true) return 0; if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) return 0; reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; dwc3_writel(dwc->regs, DWC3_DCTL, reg); do { reg = dwc3_readl(dwc->regs, DWC3_DCTL); if (!(reg & DWC3_DCTL_CSFTRST)) goto done; udelay(1); } while (--retries); phy_exit(dwc->usb3_generic_phy); phy_exit(dwc->usb2_generic_phy); return -ETIMEDOUT; done: /* * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, * we must wait at least 50ms before accessing the PHY domain * (synchronization delay). DWC_usb31 programming guide section 1.3.2. */ if (dwc3_is_usb31(dwc)) msleep(50); return 0; }
/** * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure */ static int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; int ret; /* Before Resetting PHY, put Core in Reset */ reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg |= DWC3_GCTL_CORESOFTRESET; dwc3_writel(dwc->regs, DWC3_GCTL, reg); /* Assert USB3 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); /* Assert USB2 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) return ret; ret = phy_init(dwc->usb3_generic_phy); if (ret < 0) { phy_exit(dwc->usb2_generic_phy); return ret; } mdelay(100); /* Clear USB3 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); /* Clear USB2 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); mdelay(100); /* After PHYs are stable we can take Core out of reset state */ reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_CORESOFTRESET; dwc3_writel(dwc->regs, DWC3_GCTL, reg); return 0; }
static void eth_common_init(void) { bootstage_mark(BOOTSTAGE_ID_NET_ETH_START); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) miiphy_init(); #endif #ifdef CONFIG_PHYLIB phy_init(); #endif /* * If board-specific initialization exists, call it. * If not, call a CPU-specific one */ if (board_eth_init != __def_eth_init) { if (board_eth_init(gd->bd) < 0) printf("Board Net Initialization Failed\n"); } else if (cpu_eth_init != __def_eth_init) { if (cpu_eth_init(gd->bd) < 0) printf("CPU Net Initialization Failed\n"); } else { #ifndef CONFIG_DM_ETH printf("Net Initialization Skipped\n"); #endif } }
static int ohci_da8xx_enable(struct usb_hcd *hcd) { struct da8xx_ohci_hcd *da8xx_ohci = to_da8xx_ohci(hcd); int ret; ret = clk_prepare_enable(da8xx_ohci->usb11_clk); if (ret) return ret; ret = phy_init(da8xx_ohci->usb11_phy); if (ret) goto err_phy_init; ret = phy_power_on(da8xx_ohci->usb11_phy); if (ret) goto err_phy_power_on; return 0; err_phy_power_on: phy_exit(da8xx_ohci->usb11_phy); err_phy_init: clk_disable_unprepare(da8xx_ohci->usb11_clk); return ret; }
static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) { struct platform_device *pdev = to_platform_device(hsotg->dev); int ret; ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); if (ret) return ret; if (hsotg->clk) { ret = clk_prepare_enable(hsotg->clk); if (ret) return ret; } if (hsotg->uphy) { ret = usb_phy_init(hsotg->uphy); } else if (hsotg->plat && hsotg->plat->phy_init) { ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); } else { ret = phy_power_on(hsotg->phy); if (ret == 0) ret = phy_init(hsotg->phy); } return ret; }
static int mtk_phy_connect(struct mtk_mac *mac) { struct mtk_eth *eth = mac->hw; int i; for (i = 0; i < 8; i++) { if (eth->phy->phy_node[i]) { if (!mac->phy_dev) { mac->phy_dev = eth->phy->phy[i]; mac->phy_flags = MTK_PHY_FLAG_PORT; } } else if (eth->mii_bus) { struct phy_device *phy; phy = mdiobus_get_phy(eth->mii_bus, i); if (phy) { phy_init(eth, mac, phy); if (!mac->phy_dev) { mac->phy_dev = phy; mac->phy_flags = MTK_PHY_FLAG_ATTACH; } } } } return 0; }
static int dra7xx_pcie_resume_noirq(struct device *dev) { struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); int phy_count = dra7xx->phy_count; int ret; int i; for (i = 0; i < phy_count; i++) { ret = phy_init(dra7xx->phy[i]); if (ret < 0) goto err_phy; ret = phy_power_on(dra7xx->phy[i]); if (ret < 0) { phy_exit(dra7xx->phy[i]); goto err_phy; } } return 0; err_phy: while (--i >= 0) { phy_power_off(dra7xx->phy[i]); phy_exit(dra7xx->phy[i]); } return ret; }
void vInitEmac( void ) { /* Software reset. */ prvResetMAC(); /* Set the Rx and Tx descriptors into their initial state. */ prvInitialiseDescriptors(); /* Set the MAC address into the ETHERC */ ETHERC.MAHR = ( ( unsigned long ) configMAC_ADDR0 << 24UL ) | ( ( unsigned long ) configMAC_ADDR1 << 16UL ) | ( ( unsigned long ) configMAC_ADDR2 << 8UL ) | ( unsigned long ) configMAC_ADDR3; ETHERC.MALR.BIT.MA = ( ( unsigned long ) configMAC_ADDR4 << 8UL ) | ( unsigned long ) configMAC_ADDR5; /* Perform rest of interface hardware configuration. */ prvConfigureEtherCAndEDMAC(); /* Nothing received yet, so uip_buf points nowhere. */ uip_buf = NULL; /* Initialize the PHY */ phy_init(); }
static int dwc3_resume(struct device *dev) { struct dwc3 *dwc = dev_get_drvdata(dev); unsigned long flags; int ret; pinctrl_pm_select_default_state(dev); usb_phy_init(dwc->usb3_phy); usb_phy_init(dwc->usb2_phy); ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) return ret; ret = phy_init(dwc->usb3_generic_phy); if (ret < 0) goto err_usb2phy_init; spin_lock_irqsave(&dwc->lock, flags); dwc3_event_buffers_setup(dwc); dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: case USB_DR_MODE_OTG: dwc3_gadget_resume(dwc); /* FALLTHROUGH */ case USB_DR_MODE_HOST: default: /* do nothing */ break; } spin_unlock_irqrestore(&dwc->lock, flags); pm_runtime_disable(dev); pm_runtime_set_active(dev); pm_runtime_enable(dev); return 0; err_usb2phy_init: phy_exit(dwc->usb2_generic_phy); return ret; }
static int da8xx_musb_init(struct musb *musb) { struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent); void __iomem *reg_base = musb->ctrl_base; u32 rev; int ret = -ENODEV; musb->mregs += DA8XX_MENTOR_CORE_OFFSET; ret = clk_prepare_enable(glue->clk); if (ret) { dev_err(glue->dev, "failed to enable clock\n"); return ret; } /* Returns zero if e.g. not clocked */ rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG); if (!rev) goto fail; musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); if (IS_ERR_OR_NULL(musb->xceiv)) { ret = -EPROBE_DEFER; goto fail; } setup_timer(&otg_workaround, otg_timer, (unsigned long)musb); /* Reset the controller */ musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK); /* Start the on-chip PHY and its PLL. */ ret = phy_init(glue->phy); if (ret) { dev_err(glue->dev, "Failed to init phy.\n"); goto fail; } ret = phy_power_on(glue->phy); if (ret) { dev_err(glue->dev, "Failed to power on phy.\n"); goto err_phy_power_on; } msleep(5); /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */ pr_debug("DA8xx OTG revision %08x, control %02x\n", rev, musb_readb(reg_base, DA8XX_USB_CTRL_REG)); musb->isr = da8xx_musb_interrupt; return 0; err_phy_power_on: phy_exit(glue->phy); fail: clk_disable_unprepare(glue->clk); return ret; }
void hdmirx_hw_reset(void) { hdmirx_print("%s %d\n", __func__, rx.port); //WRITE_CBUS_REG(RESET0_REGISTER, 0x8); //reset HDMIRX module //mdelay(10); //clk_init(); hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0); //disable top interrupt gate hdmirx_wr_top( HDMIRX_TOP_SW_RESET, 0x3f); mdelay(1); control_reset(0); hdmirx_wr_top( HDMIRX_TOP_PORT_SEL, (1<<rx.port)); //EDID port select hdmirx_interrupts_cfg(false); //disable dwc interrupt if(hdcp_enable){ hdmi_rx_ctrl_hdcp_config(&rx.hdcp); } else { hdmirx_wr_bits_dwc( RA_HDCP_CTRL, HDCP_ENABLE, 0); } /*phy config*/ //hdmirx_phy_restart(); //hdmi_rx_phy_fast_switching(1); phy_init(rx.port, 0); //port, dcm /**/ /* control config */ control_init(rx.port); audio_init(); packet_init(); hdmirx_audio_fifo_rst(); hdmirx_packet_fifo_rst(); /**/ control_reset(1); /*enable irq */ hdmirx_wr_top(HDMIRX_TOP_INTR_STAT_CLR, ~0); hdmirx_wr_top(HDMIRX_TOP_INTR_MASKN, 0x00001fff); hdmirx_interrupts_hpd(true); /**/ #ifndef USE_GPIO_FOR_HPD hdmi_rx_ctrl_hpd(true); hdmirx_wr_top( HDMIRX_TOP_HPD_PWR5V, (1<<5)|(1<<4)); //invert HDP output #endif /* wait at least 4 video frames (at 24Hz) : 167ms for the mode detection recover the video mode */ mdelay(200); /* Check If HDCP engine is in Idle state, if not wait for authentication time. 200ms is enough if no Ri errors */ if (hdmirx_rd_dwc(0xe0) != 0) { mdelay(200); } }
void main() { system_init(buffer, sizeof(buffer), buffer, sizeof(buffer)); phy_init(); int p = cc1101_interface_read_single_reg(PARTNUM); p = cc1101_interface_read_single_reg(VERSION); cc1101_interface_strobe(RF_STX); while(1); }
/** * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure */ static int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; int retries = 1000; int ret; usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) return ret; ret = phy_init(dwc->usb3_generic_phy); if (ret < 0) { phy_exit(dwc->usb2_generic_phy); return ret; } /* * We're resetting only the device side because, if we're in host mode, * XHCI driver will reset the host block. If dwc3 was configured for * host-only mode, then we can return early. */ if (dwc->dr_mode == USB_DR_MODE_HOST) return 0; reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; dwc3_writel(dwc->regs, DWC3_DCTL, reg); do { reg = dwc3_readl(dwc->regs, DWC3_DCTL); if (!(reg & DWC3_DCTL_CSFTRST)) return 0; udelay(1); } while (--retries); return -ETIMEDOUT; }
static int st_ehci_platform_power_on(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct st_ehci_platform_priv *priv = hcd_to_ehci_priv(hcd); int clk, ret; ret = reset_control_deassert(priv->pwr); if (ret) return ret; ret = reset_control_deassert(priv->rst); if (ret) goto err_assert_power; /* some SoCs don't have a dedicated 48Mhz clock, but those that do need the rate to be explicitly set */ if (priv->clk48) { ret = clk_set_rate(priv->clk48, 48000000); if (ret) goto err_assert_reset; } for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { ret = clk_prepare_enable(priv->clks[clk]); if (ret) goto err_disable_clks; } ret = phy_init(priv->phy); if (ret) goto err_disable_clks; ret = phy_power_on(priv->phy); if (ret) goto err_exit_phy; return 0; err_exit_phy: phy_exit(priv->phy); err_disable_clks: while (--clk >= 0) clk_disable_unprepare(priv->clks[clk]); err_assert_reset: reset_control_assert(priv->rst); err_assert_power: reset_control_assert(priv->pwr); return ret; }
static int omap2430_runtime_resume(struct device *dev) { struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); if (!musb) return 0; phy_init(musb->phy); phy_power_on(musb->phy); omap2430_low_level_init(musb); musb_writel(musb->mregs, OTG_INTERFSEL, musb->context.otg_interfsel); return 0; }
static int ssusb_phy_init(struct ssusb_mtk *ssusb) { int i; int ret; for (i = 0; i < ssusb->num_phys; i++) { ret = phy_init(ssusb->phys[i]); if (ret) goto exit_phy; } return 0; exit_phy: for (; i > 0; i--) phy_exit(ssusb->phys[i - 1]); return ret; }
static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk) { int i; int ret; for (i = 0; i < mtk->num_phys; i++) { ret = phy_init(mtk->phys[i]); if (ret) goto exit_phy; } return 0; exit_phy: for (; i > 0; i--) phy_exit(mtk->phys[i - 1]); return ret; }
//does not turn on radio. void mac_init() { // Initialize send queue queue_init(&mac_send_queue); // Initialize PHY layer phy_init(); mac_state = MAC_STATE_IDLE; mac_set_tx_idle(); // PIB mac_pib.macPANID = RADIO_DEFAULT_PANID; mac_pib.macSAddr = SHORTADDRL; mac_pib.macSAddr += (SHORTADDRH << 8); // Initialize mhr mac_init_mhr(); }
static int ahci_resume(struct device *dev) { struct ahci_platform_data *pdata = dev_get_platdata(dev); struct ata_host *host = dev_get_drvdata(dev); struct ahci_host_priv *hpriv = host->private_data; int rc; if (!IS_ERR(hpriv->clk)) { rc = clk_prepare_enable(hpriv->clk); if (rc) { dev_err(dev, "clock prepare enable failed"); return rc; } } if (!IS_ERR(hpriv->phy)) { phy_init(hpriv->phy); phy_power_on(hpriv->phy); } if (pdata && pdata->resume) { rc = pdata->resume(dev); if (rc) goto disable_unprepare_clk; } if (dev->power.power_state.event == PM_EVENT_SUSPEND) { rc = ahci_reset_controller(host); if (rc) goto disable_unprepare_clk; ahci_init_controller(host); } ata_host_resume(host); return 0; disable_unprepare_clk: if (!IS_ERR(hpriv->clk)) clk_disable_unprepare(hpriv->clk); return rc; }
static int ehci_platform_power_on(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd); int clk, ret, phy_num; for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) { ret = clk_prepare_enable(priv->clks[clk]); if (ret) goto err_disable_clks; } for (phy_num = 0; phy_num < priv->num_phys; phy_num++) { if (priv->phys[phy_num]) { ret = phy_init(priv->phys[phy_num]); if (ret) goto err_exit_phy; ret = phy_power_on(priv->phys[phy_num]); if (ret) { phy_exit(priv->phys[phy_num]); goto err_exit_phy; } } } return 0; err_exit_phy: while (--phy_num >= 0) { if (priv->phys[phy_num]) { phy_power_off(priv->phys[phy_num]); phy_exit(priv->phys[phy_num]); } } err_disable_clks: while (--clk >= 0) clk_disable_unprepare(priv->clks[clk]); return ret; }
/* * return 0: successful * return -1: lane count error * return -2: res cal error * return -3: dp sink init error */ int edp_init(unsigned int lane_cnt, unsigned int bit_rate) { int try_cnt = 0; if(lane_cnt > MAX_LANE_NUM) return -1; phy_init(lane_cnt,bit_rate); phy_res_cal(); phy_cfg(0,0,0); dp_ctrl_init(); while(dp_sink_init()) { try_cnt ++; edp_delay_ms(50); if(try_cnt >= 3) return -3; } return 0; }
static int msm_ahci_init_phy(struct msm_ahci_host *host) { int ret = 0; struct device *dev = host->ahci_pdev->dev.parent; host->phy = devm_phy_get(dev, "sata-6g"); if (IS_ERR(host->phy)) { ret = PTR_ERR(host->phy); dev_err(dev, "PHY get failed %d\n", ret); goto out; } ret = phy_init(host->phy); if (ret) { dev_err(dev, "PHY initialization failed %d\n", ret); goto out; } ret = phy_power_on(host->phy); if (ret) { dev_err(dev, "PHY power on failed %d\n", ret); goto out; } host->phy_powered_on = true; /* asic0 and rbc0 clks needs to be ungated only after phy power on */ ret = msm_ahci_setup_asic_rbc_clks(host, true); if (ret) { dev_err(dev, "failed to enable asic0/rbc0 clks %d", ret); goto out; } out: return ret; }
/** * ahci_platform_enable_resources - Enable platform resources * @hpriv: host private area to store config values * * This function enables all ahci_platform managed resources in the * following order: * 1) Regulator * 2) Clocks (through ahci_platform_enable_clks) * 3) Phy * * If resource enabling fails at any point the previous enabled resources * are disabled in reverse order. * * RETURNS: * 0 on success otherwise a negative error code */ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv) { int rc; if (hpriv->target_pwr) { rc = regulator_enable(hpriv->target_pwr); if (rc) return rc; } rc = ahci_platform_enable_clks(hpriv); if (rc) goto disable_regulator; if (hpriv->phy) { rc = phy_init(hpriv->phy); if (rc) goto disable_clks; rc = phy_power_on(hpriv->phy); if (rc) { phy_exit(hpriv->phy); goto disable_clks; } } return 0; disable_clks: ahci_platform_disable_clks(hpriv); disable_regulator: if (hpriv->target_pwr) regulator_disable(hpriv->target_pwr); return rc; }
static int exynos_pcie_establish_link(struct exynos_pcie *ep) { struct dw_pcie *pci = ep->pci; struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; if (dw_pcie_link_up(pci)) { dev_err(dev, "Link already up\n"); return 0; } exynos_pcie_assert_core_reset(ep); phy_reset(ep->phy); exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET); phy_power_on(ep->phy); phy_init(ep->phy); exynos_pcie_deassert_core_reset(ep); dw_pcie_setup_rc(pp); exynos_pcie_assert_reset(ep); /* assert LTSSM enable */ exynos_pcie_writel(ep->mem_res->elbi_base, PCIE_ELBI_LTSSM_ENABLE, PCIE_APP_LTSSM_ENABLE); /* check if the link is up or not */ if (!dw_pcie_wait_for_link(pci)) return 0; phy_power_off(ep->phy); return -ETIMEDOUT; }
static int exynos_ehci_attach(device_t dev) { struct exynos_ehci_softc *esc; ehci_softc_t *sc; bus_space_handle_t bsh; int err; esc = device_get_softc(dev); esc->dev = dev; sc = &esc->base; sc->sc_bus.parent = dev; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; if (bus_alloc_resources(dev, exynos_ehci_spec, esc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* EHCI registers */ sc->sc_io_tag = rman_get_bustag(esc->res[0]); bsh = rman_get_bushandle(esc->res[0]); sc->sc_io_size = rman_get_size(esc->res[0]); /* EHCI HOST ctrl registers */ esc->host_bst = rman_get_bustag(esc->res[1]); esc->host_bsh = rman_get_bushandle(esc->res[1]); /* PWR registers */ esc->pwr_bst = rman_get_bustag(esc->res[2]); esc->pwr_bsh = rman_get_bushandle(esc->res[2]); /* SYSREG */ esc->sysreg_bst = rman_get_bustag(esc->res[3]); esc->sysreg_bsh = rman_get_bushandle(esc->res[3]); /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), &ehci_iterate_hw_softc)) return (ENXIO); /* * Set handle to USB related registers subregion used by * generic EHCI driver. */ err = bus_space_subregion(sc->sc_io_tag, bsh, 0x0, sc->sc_io_size, &sc->sc_io_hdl); if (err != 0) return (ENXIO); phy_init(esc); /* Setup interrupt handler */ err = bus_setup_intr(dev, esc->res[4], INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(dev, "Could not setup irq, " "%d\n", err); return (1); } /* Add USB device */ sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(dev, "Could not add USB device\n"); err = bus_teardown_intr(dev, esc->res[4], sc->sc_intr_hdl); if (err) device_printf(dev, "Could not tear down irq," " %d\n", err); return (1); } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); strlcpy(sc->sc_vendor, "Samsung", sizeof(sc->sc_vendor)); err = ehci_init(sc); if (!err) { sc->sc_flags |= EHCI_SCFLG_DONEINIT; err = device_probe_and_attach(sc->sc_bus.bdev); } else { device_printf(dev, "USB init failed err=%d\n", err); device_delete_child(dev, sc->sc_bus.bdev); sc->sc_bus.bdev = NULL; err = bus_teardown_intr(dev, esc->res[4], sc->sc_intr_hdl); if (err) device_printf(dev, "Could not tear down irq," " %d\n", err); return (1); } return (0); }
static int __init dra7xx_pcie_probe(struct platform_device *pdev) { u32 reg; int ret; int irq; int i; int phy_count; struct phy **phy; void __iomem *base; struct resource *res; struct dra7xx_pcie *dra7xx; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; char name[10]; int gpio_sel; enum of_gpio_flags flags; unsigned long gpio_flags; dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL); if (!dra7xx) return -ENOMEM; irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource\n"); return -EINVAL; } ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler, IRQF_SHARED, "dra7xx-pcie-main", dra7xx); if (ret) { dev_err(dev, "failed to request irq\n"); return ret; } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf"); base = devm_ioremap_nocache(dev, res->start, resource_size(res)); if (!base) return -ENOMEM; phy_count = of_property_count_strings(np, "phy-names"); if (phy_count < 0) { dev_err(dev, "unable to find the strings\n"); return phy_count; } phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL); if (!phy) return -ENOMEM; for (i = 0; i < phy_count; i++) { snprintf(name, sizeof(name), "pcie-phy%d", i); phy[i] = devm_phy_get(dev, name); if (IS_ERR(phy[i])) return PTR_ERR(phy[i]); ret = phy_init(phy[i]); if (ret < 0) goto err_phy; ret = phy_power_on(phy[i]); if (ret < 0) { phy_exit(phy[i]); goto err_phy; } } dra7xx->base = base; dra7xx->phy = phy; dra7xx->dev = dev; dra7xx->phy_count = phy_count; pm_runtime_enable(dev); ret = pm_runtime_get_sync(dev); if (ret < 0) { dev_err(dev, "pm_runtime_get_sync failed\n"); goto err_get_sync; } gpio_sel = of_get_gpio_flags(dev->of_node, 0, &flags); if (gpio_is_valid(gpio_sel)) { gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH; ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags, "pcie_reset"); if (ret) { dev_err(&pdev->dev, "gpio%d request failed, ret %d\n", gpio_sel, ret); goto err_gpio; } } else if (gpio_sel == -EPROBE_DEFER) { ret = -EPROBE_DEFER; goto err_gpio; } reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD); reg &= ~LTSSM_EN; dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); platform_set_drvdata(pdev, dra7xx); ret = dra7xx_add_pcie_port(dra7xx, pdev); if (ret < 0) goto err_gpio; return 0; err_gpio: pm_runtime_put(dev); err_get_sync: pm_runtime_disable(dev); err_phy: while (--i >= 0) { phy_power_off(phy[i]); phy_exit(phy[i]); } return ret; }
static int dsps_musb_init(struct musb *musb) { struct device *dev = musb->controller; struct dsps_glue *glue = dev_get_drvdata(dev->parent); struct platform_device *parent = to_platform_device(dev->parent); const struct dsps_musb_wrapper *wrp = glue->wrp; void __iomem *reg_base; struct resource *r; u32 rev, val; int ret; r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control"); reg_base = devm_ioremap_resource(dev, r); if (IS_ERR(reg_base)) return PTR_ERR(reg_base); musb->ctrl_base = reg_base; /* NOP driver needs change if supporting dual instance */ musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0); if (IS_ERR(musb->xceiv)) return PTR_ERR(musb->xceiv); musb->phy = devm_phy_get(dev->parent, "usb2-phy"); /* Returns zero if e.g. not clocked */ rev = musb_readl(reg_base, wrp->revision); if (!rev) return -ENODEV; if (IS_ERR(musb->phy)) { musb->phy = NULL; } else { ret = phy_init(musb->phy); if (ret < 0) return ret; ret = phy_power_on(musb->phy); if (ret) { phy_exit(musb->phy); return ret; } } timer_setup(&musb->dev_timer, otg_timer, 0); /* Reset the musb */ musb_writel(reg_base, wrp->control, (1 << wrp->reset)); musb->isr = dsps_interrupt; /* reset the otgdisable bit, needed for host mode to work */ val = musb_readl(reg_base, wrp->phy_utmi); val &= ~(1 << wrp->otg_disable); musb_writel(musb->ctrl_base, wrp->phy_utmi, val); /* * Check whether the dsps version has babble control enabled. * In latest silicon revision the babble control logic is enabled. * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control * logic enabled. */ val = musb_readb(musb->mregs, MUSB_BABBLE_CTL); if (val & MUSB_BABBLE_RCV_DISABLE) { glue->sw_babble_enabled = true; val |= MUSB_BABBLE_SW_SESSION_CTRL; musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val); } dsps_mod_timer(glue, -1); return dsps_musb_dbg_init(musb, glue); }
static int vybrid_ehci_attach(device_t dev) { struct vybrid_ehci_softc *esc; ehci_softc_t *sc; bus_space_handle_t bsh; int err; int reg; esc = device_get_softc(dev); esc->dev = dev; sc = &esc->base; sc->sc_bus.parent = dev; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; if (bus_alloc_resources(dev, vybrid_ehci_spec, esc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* EHCI registers */ sc->sc_io_tag = rman_get_bustag(esc->res[0]); bsh = rman_get_bushandle(esc->res[0]); sc->sc_io_size = rman_get_size(esc->res[0]); esc->bst_usbc = rman_get_bustag(esc->res[1]); esc->bsh_usbc = rman_get_bushandle(esc->res[1]); esc->bst_phy = rman_get_bustag(esc->res[2]); esc->bsh_phy = rman_get_bushandle(esc->res[2]); /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), &ehci_iterate_hw_softc)) return (ENXIO); #if 0 printf("USBx_HCSPARAMS is 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_HCSPARAMS)); printf("USB_ID == 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_ID)); printf("USB_HWGENERAL == 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_HWGENERAL)); printf("USB_HWHOST == 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_HWHOST)); printf("USB_HWDEVICE == 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_HWDEVICE)); printf("USB_HWTXBUF == 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_HWTXBUF)); printf("USB_HWRXBUF == 0x%08x\n", bus_space_read_4(sc->sc_io_tag, bsh, USB_HWRXBUF)); #endif if (phy_init(esc)) { device_printf(dev, "Could not setup PHY\n"); return (1); } /* * Set handle to USB related registers subregion used by * generic EHCI driver. */ err = bus_space_subregion(sc->sc_io_tag, bsh, 0x100, sc->sc_io_size, &sc->sc_io_hdl); if (err != 0) return (ENXIO); /* Setup interrupt handler */ err = bus_setup_intr(dev, esc->res[3], INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(dev, "Could not setup irq, " "%d\n", err); return (1); } /* Add USB device */ sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(dev, "Could not add USB device\n"); err = bus_teardown_intr(dev, esc->res[5], sc->sc_intr_hdl); if (err) device_printf(dev, "Could not tear down irq," " %d\n", err); return (1); } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); strlcpy(sc->sc_vendor, "Freescale", sizeof(sc->sc_vendor)); /* Set host mode */ reg = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl, 0xA8); reg |= 0x3; bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, 0xA8, reg); /* Set flags */ sc->sc_flags |= EHCI_SCFLG_SETMODE | EHCI_SCFLG_NORESTERM; err = ehci_init(sc); if (!err) { sc->sc_flags |= EHCI_SCFLG_DONEINIT; err = device_probe_and_attach(sc->sc_bus.bdev); } else { device_printf(dev, "USB init failed err=%d\n", err); device_delete_child(dev, sc->sc_bus.bdev); sc->sc_bus.bdev = NULL; err = bus_teardown_intr(dev, esc->res[5], sc->sc_intr_hdl); if (err) device_printf(dev, "Could not tear down irq," " %d\n", err); return (1); } return (0); }
static int omap2430_musb_init(struct musb *musb) { u32 l; int status = 0; struct device *dev = musb->controller; struct omap2430_glue *glue = dev_get_drvdata(dev->parent); struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); struct omap_musb_board_data *data = plat->board_data; /* We require some kind of external transceiver, hooked * up through ULPI. TWL4030-family PMICs include one, * which needs a driver, drivers aren't always needed. */ if (dev->parent->of_node) { musb->phy = devm_phy_get(dev->parent, "usb2-phy"); /* We can't totally remove musb->xceiv as of now because * musb core uses xceiv.state and xceiv.otg. Once we have * a separate state machine to handle otg, these can be moved * out of xceiv and then we can start using the generic PHY * framework */ musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0); } else { musb->xceiv = devm_usb_get_phy_dev(dev, 0); musb->phy = devm_phy_get(dev, "usb"); } if (IS_ERR(musb->xceiv)) { status = PTR_ERR(musb->xceiv); if (status == -ENXIO) return status; dev_dbg(dev, "HS USB OTG: no transceiver configured\n"); return -EPROBE_DEFER; } if (IS_ERR(musb->phy)) { dev_err(dev, "HS USB OTG: no PHY configured\n"); return PTR_ERR(musb->phy); } musb->isr = omap2430_musb_interrupt; phy_init(musb->phy); phy_power_on(musb->phy); l = musb_readl(musb->mregs, OTG_INTERFSEL); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */ l &= ~ULPI_12PIN; /* Disable ULPI */ l |= UTMI_8BIT; /* Enable UTMI */ } else { l |= ULPI_12PIN; } musb_writel(musb->mregs, OTG_INTERFSEL, l); dev_dbg(dev, "HS USB OTG: revision 0x%x, sysconfig 0x%02x, " "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", musb_readl(musb->mregs, OTG_REVISION), musb_readl(musb->mregs, OTG_SYSCONFIG), musb_readl(musb->mregs, OTG_SYSSTATUS), musb_readl(musb->mregs, OTG_INTERFSEL), musb_readl(musb->mregs, OTG_SIMENABLE)); if (glue->status != MUSB_UNKNOWN) omap_musb_set_mailbox(glue); return 0; }
static int histb_pcie_probe(struct platform_device *pdev) { struct histb_pcie *hipcie; struct dw_pcie *pci; struct pcie_port *pp; struct resource *res; struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; enum of_gpio_flags of_flags; unsigned long flag = GPIOF_DIR_OUT; int ret; hipcie = devm_kzalloc(dev, sizeof(*hipcie), GFP_KERNEL); if (!hipcie) return -ENOMEM; pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); if (!pci) return -ENOMEM; hipcie->pci = pci; pp = &pci->pp; pci->dev = dev; pci->ops = &dw_pcie_ops; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); hipcie->ctrl = devm_ioremap_resource(dev, res); if (IS_ERR(hipcie->ctrl)) { dev_err(dev, "cannot get control reg base\n"); return PTR_ERR(hipcie->ctrl); } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc-dbi"); pci->dbi_base = devm_ioremap_resource(dev, res); if (IS_ERR(pci->dbi_base)) { dev_err(dev, "cannot get rc-dbi base\n"); return PTR_ERR(pci->dbi_base); } hipcie->vpcie = devm_regulator_get_optional(dev, "vpcie"); if (IS_ERR(hipcie->vpcie)) { if (PTR_ERR(hipcie->vpcie) == -EPROBE_DEFER) return -EPROBE_DEFER; hipcie->vpcie = NULL; } hipcie->reset_gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &of_flags); if (of_flags & OF_GPIO_ACTIVE_LOW) flag |= GPIOF_ACTIVE_LOW; if (gpio_is_valid(hipcie->reset_gpio)) { ret = devm_gpio_request_one(dev, hipcie->reset_gpio, flag, "PCIe device power control"); if (ret) { dev_err(dev, "unable to request gpio\n"); return ret; } } hipcie->aux_clk = devm_clk_get(dev, "aux"); if (IS_ERR(hipcie->aux_clk)) { dev_err(dev, "Failed to get PCIe aux clk\n"); return PTR_ERR(hipcie->aux_clk); } hipcie->pipe_clk = devm_clk_get(dev, "pipe"); if (IS_ERR(hipcie->pipe_clk)) { dev_err(dev, "Failed to get PCIe pipe clk\n"); return PTR_ERR(hipcie->pipe_clk); } hipcie->sys_clk = devm_clk_get(dev, "sys"); if (IS_ERR(hipcie->sys_clk)) { dev_err(dev, "Failed to get PCIEe sys clk\n"); return PTR_ERR(hipcie->sys_clk); } hipcie->bus_clk = devm_clk_get(dev, "bus"); if (IS_ERR(hipcie->bus_clk)) { dev_err(dev, "Failed to get PCIe bus clk\n"); return PTR_ERR(hipcie->bus_clk); } hipcie->soft_reset = devm_reset_control_get(dev, "soft"); if (IS_ERR(hipcie->soft_reset)) { dev_err(dev, "couldn't get soft reset\n"); return PTR_ERR(hipcie->soft_reset); } hipcie->sys_reset = devm_reset_control_get(dev, "sys"); if (IS_ERR(hipcie->sys_reset)) { dev_err(dev, "couldn't get sys reset\n"); return PTR_ERR(hipcie->sys_reset); } hipcie->bus_reset = devm_reset_control_get(dev, "bus"); if (IS_ERR(hipcie->bus_reset)) { dev_err(dev, "couldn't get bus reset\n"); return PTR_ERR(hipcie->bus_reset); } if (IS_ENABLED(CONFIG_PCI_MSI)) { pp->msi_irq = platform_get_irq_byname(pdev, "msi"); if (pp->msi_irq < 0) { dev_err(dev, "Failed to get MSI IRQ\n"); return pp->msi_irq; } } hipcie->phy = devm_phy_get(dev, "phy"); if (IS_ERR(hipcie->phy)) { dev_info(dev, "no pcie-phy found\n"); hipcie->phy = NULL; /* fall through here! * if no pcie-phy found, phy init * should be done under boot! */ } else { phy_init(hipcie->phy); } pp->root_bus_nr = -1; pp->ops = &histb_pcie_host_ops; platform_set_drvdata(pdev, hipcie); ret = histb_pcie_host_enable(pp); if (ret) { dev_err(dev, "failed to enable host\n"); return ret; } ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; } return 0; }