static int isp_release(struct inode *inode, struct file *filp)
{
struct isp_t *dev = (struct isp_t *) filp->private_data;
free_irq(IRQ_ISP, dev);
pi_mgr_qos_request_update(&isp_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
#ifndef CONFIG_ARCH_JAVA
scu_standby(1);
#endif
disable_isp_clock();
if (pi_mgr_dfs_request_update(&isp_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk(KERN_ERR "%s: failed to update dfs request for isp\n",
__func__);
}
pi_mgr_dfs_request_remove(&isp_dfs_node);
isp_dfs_node.name = NULL;
pi_mgr_qos_request_remove(&isp_qos_node);
isp_qos_node.name = NULL;
mutex_lock(&brcm_global_isp_lock);
brcm_global_isp_in_use--;
mutex_unlock(&brcm_global_isp_lock);
kfree(dev);
return 0;
}
static int isp_open(struct inode *inode, struct file *filp)
{
int ret = 0;
struct isp_t *dev = kmalloc(sizeof(struct isp_t), GFP_KERNEL);
if (!dev)
return -ENOMEM;
filp->private_data = dev;
spin_lock_init(&dev->lock);
dev->isp_status.status = 0;
init_completion(&dev->irq_sem);
ret =
pi_mgr_dfs_add_request(&isp_dfs_node, "isp", PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI DFS request\n",
__func__);
goto err;
}
ret = pi_mgr_qos_add_request(&isp_qos_node, "isp",
PI_MGR_PI_ID_ARM_CORE,
PI_MGR_QOS_DEFAULT_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
goto qos_request_fail;
}
enable_isp_clock();
pi_mgr_qos_request_update(&isp_qos_node, 0);
scu_standby(0);
ret =
request_irq(IRQ_ISP, isp_isr, IRQF_DISABLED | IRQF_SHARED,
ISP_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(IRQ_ISP, cpumask_of(0));
disable_irq(IRQ_ISP);
return 0;
qos_request_fail:
pi_mgr_dfs_request_remove(&isp_dfs_node);
err:
kfree(dev);
return ret;
}
static void _power_off(void)
{
int s;
/* Platform specific power-off procedure. May be that this
*should be in a separate file? TODO: REVIEWME */
s = pi_mgr_dfs_request_remove(&vce_state.dfs_node);
BUG_ON(s != 0);
vce_state.dfs_node.name = NULL;
}
static void unicam_put_clocks(struct unicam_device *unicam)
{
int r;
if (unicam->csi2_axi_clk) {
clk_put(unicam->csi2_axi_clk);
unicam->csi2_axi_clk = NULL;
}
if (unicam->dfs_client.valid) {
r = pi_mgr_dfs_request_remove(&unicam->dfs_client);
if (r)
dev_err(unicam->dev, "failed to remove dfs request\n");
}
}
static int h264_release(struct inode *inode, struct file *filp)
{
struct h264_t *dev = (struct h264_t *) filp->private_data;
/*
Restore the default QOS value.
Restore the minimum value for DVFS
Removes the request for DFS and QOS
Disables the clock.
*/
#ifdef H264_CLK_MGMT
#ifdef H264_QOS_MGMT
pi_mgr_qos_request_update(&h264_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
scu_standby(1);
#endif
disable_h264_clock();
if (pi_mgr_dfs_request_update(&h264_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk(KERN_ERR "%s: failed to update dfs request for h264\n",
__func__);
}
pi_mgr_dfs_request_remove(&h264_dfs_node);
h264_dfs_node.name = NULL;
#ifdef H264_QOS_MGMT
pi_mgr_qos_request_remove(&h264_qos_node);
h264_qos_node.name = NULL;
#endif
#endif
#ifdef ENABLE_H264_INT
free_irq(H264_AOB_IRQ, dev);
free_irq(H264_CME_IRQ, dev);
free_irq(H264_MCIN_CBC_IRQ, dev);
#endif
kfree(dev);
mutex_unlock(&h264_mutex);
return 0;
}
static int isp2_release(struct inode *inode, struct file *filp)
{
struct isp2_t *dev = (struct isp2_t *) filp->private_data;
pi_mgr_qos_request_update(&isp2_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
disable_isp2_clock();
if (pi_mgr_dfs_request_update(&isp2_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk(KERN_ERR "%s: failed to update dfs request for isp2\n",
__func__);
}
pi_mgr_dfs_request_remove(&isp2_dfs_node);
isp2_dfs_node.name = NULL;
pi_mgr_qos_request_remove(&isp2_qos_node);
isp2_qos_node.name = NULL;
free_irq(IRQ_ISP2, dev);
kfree(dev);
return 0;
}
static int h264_open(struct inode *inode, struct file *filp)
{
int ret = 0;
struct h264_t *dev = kmalloc(sizeof(struct h264_t), GFP_KERNEL);
if (!dev) {
printk("\n Returning from no memory");
return -ENOMEM;
}
mutex_lock(&h264_mutex);
filp->private_data = dev;
spin_lock_init(&dev->lock);
dev->dev_status.cbc_intr = 0x00;
dev->dev_status.mcin_intr = 0x00;
init_completion(&dev->irq_sem);
/*
Add a request for DFS.
Add a request for QOS (with default value)
Enable the clock for H.264 block.
*/
#ifdef H264_CLK_MGMT
ret =
pi_mgr_dfs_add_request(&h264_dfs_node, "h264", PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI DFS request\n",
__func__);
goto err;
}
#ifdef H264_QOS_MGMT
ret =
pi_mgr_qos_add_request(&h264_qos_node, "h264",
PI_MGR_PI_ID_ARM_CORE,
PI_MGR_QOS_DEFAULT_VALUE);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
goto qos_request_fail;
}
#endif
enable_h264_clock();
/* Access to root reset manager register block. */
writel(0xa5a501, IOMEM(HW_IO_PHYS_TO_VIRT(0x35001f00)));
usleep_range(10, 20);
/* Enable multimedia power domain. */
/* Test 0x3d should be sufficient for MM. */
writel(0xfd, IOMEM(HW_IO_PHYS_TO_VIRT(0x35001f08)));
usleep_range(10, 20);
/* Enable H264 Slave interface control register. */
writel(0x00, IOMEM(HW_IO_PHYS_TO_VIRT(0x3C00F004)));
usleep_range(10, 20);
/* Enable H264 Master interface control register. */
writel(0x00, IOMEM(HW_IO_PHYS_TO_VIRT(0x3C00F008)));
usleep_range(10, 20);
#ifdef H264_QOS_MGMT
ret = pi_mgr_qos_request_update(&h264_qos_node, 0);
if (ret) {
printk(KERN_ERR "%s: failed to register PI QOS request\n",
__func__);
ret = -EIO;
}
scu_standby(0);
#endif
#endif
usleep_range(50, 100); /* buffer to ensure everything above are done. */
#ifdef ENABLE_H264_INT
/* Register for the interrupts */
ret =
request_irq(H264_AOB_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED |
IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for AOB ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_AOB_IRQ, cpumask_of(0));
ret =
request_irq(H264_CME_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED |
IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for CME ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_CME_IRQ, cpumask_of(0));
ret =
request_irq(H264_MCIN_CBC_IRQ, h264_isr, IRQF_DISABLED | IRQF_SHARED
| IRQF_NO_SUSPEND, H264_DEV_NAME, dev);
if (ret) {
err_print("request_irq failed for MCIN_CBC ret = %d\n", ret);
goto err;
}
/* Ensure that only one CORE handles interrupt for the MM block. */
irq_set_affinity(H264_MCIN_CBC_IRQ, cpumask_of(0));
disable_irq(H264_AOB_IRQ);
disable_irq(H264_CME_IRQ);
disable_irq(H264_MCIN_CBC_IRQ);
#endif
return 0;
#ifdef H264_QOS_MGMT
qos_request_fail:
pi_mgr_dfs_request_remove(&h264_dfs_node);
#endif
err:
kfree(dev);
printk(KERN_ERR "\nError in the h264_open\n");
mutex_unlock(&h264_mutex);
return ret;
}
