/*
* unicam_enable_clocks - Enable unicam clocks
* @unicam: KONA Unicam device
* Return 0 if successful, or clk_enable return value
*/
static int unicam_enable_clocks(struct unicam_device *unicam)
{
int r;
r = pi_mgr_dfs_request_update(&unicam->dfs_client, PI_OPP_TURBO);
if (r) {
dev_err(unicam->dev, "failed to update dfs request(turbo)\n");
return r;
}
r = clk_enable(unicam->csi2_axi_clk);
if (r) {
dev_err(unicam->dev, "clk_enable csi2_axi_clk failed\n");
goto err_clk_enable;
}
return 0;
err_clk_enable:
if (pi_mgr_dfs_request_update(&unicam->dfs_client,
PI_MGR_DFS_MIN_VALUE))
dev_err(unicam->dev, "failed to update dfs request(min)\n");
return r;
}
static int hawaii_camera_power(struct device *dev, int on)
{
static struct pi_mgr_dfs_node unicam_dfs_node;
int ret;
printk(KERN_INFO "%s:camera power %s, %d\n", __func__,
(on ? "on" : "off"), unicam_dfs_node.valid);
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
printk(
KERN_ERR "%s: failed to register PI DFS request\n",
__func__
);
return -1;
}
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO)) {
printk(
KERN_ERR "%s:failed to update dfs request for unicam\n",
__func__
);
return -1;
}
}
if (!camdrv_ss_power(0, (bool)on)) {
printk(
KERN_ERR "%s,camdrv_ss_power failed for MAIN CAM!!\n",
__func__
);
return -1;
}
if (!on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node,
PI_MGR_DFS_MIN_VALUE)) {
printk(
KERN_ERR"%s: failed to update dfs request for unicam\n",
__func__);
}
}
return 0;
}
int brcm_enable_dsi_lcd_clocks(
struct pi_mgr_dfs_node* dfs_node,
unsigned int dsi_bus,
unsigned int dsi_pll_hz,
unsigned int dsi_pll_ch_div,
unsigned int esc_clk_hz )
{
printk("[LCD] %s : g_display_enabled ==> %d\n", __func__, g_display_enabled);
#ifndef CONFIG_MACH_BCM_FPGA
if (pi_mgr_dfs_request_update(dfs_node, PI_OPP_ECONOMY)) {
printk(KERN_ERR "Failed to update dfs request for DSI LCD\n");
return -EIO;
}
if (g_display_enabled) {
dsi_axi_clk(dsi_bus, true);
printk(KERN_ERR "Skipping dsi_axi_clk\n");
}
dsi_esc_clk(dsi_bus, esc_clk_hz, true);
#endif
return 0;
}
int brcm_enable_smi_lcd_clocks(struct pi_mgr_dfs_node *dfs_node)
{
#ifndef CONFIG_MACH_BCM_FPGA
struct clk *smi_axi;
struct clk *smi;
if (pi_mgr_dfs_request_update(dfs_node, PI_OPP_ECONOMY)) {
printk(KERN_ERR "Failed to update dfs request for SMI LCD at enable\n");
return -EIO;
}
smi_axi = clk_get (NULL, "smi_axi_clk");
smi = clk_get (NULL, "smi_clk");
BUG_ON(IS_ERR_OR_NULL(smi_axi) || IS_ERR_OR_NULL(smi));
if (clk_set_rate(smi, 250000000)) {
printk(KERN_ERR "Failed to set the SMI peri clock to 250MHZ");
return -EIO;
}
if (clk_enable(smi)) {
printk(KERN_ERR "Failed to enable the SMI peri clock");
return -EIO;
}
if (clk_enable (smi_axi)) {
printk(KERN_ERR "Failed to enable the SMI bus clock");
return -EIO;
}
#endif
return 0;
}
static int isp_release(struct inode *inode, struct file *filp)
{
struct isp_t *dev = (struct isp_t *) filp->private_data;
free_irq(IRQ_ISP, dev);
pi_mgr_qos_request_update(&isp_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
#ifndef CONFIG_ARCH_JAVA
scu_standby(1);
#endif
disable_isp_clock();
if (pi_mgr_dfs_request_update(&isp_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk(KERN_ERR "%s: failed to update dfs request for isp\n",
__func__);
}
pi_mgr_dfs_request_remove(&isp_dfs_node);
isp_dfs_node.name = NULL;
pi_mgr_qos_request_remove(&isp_qos_node);
isp_qos_node.name = NULL;
mutex_lock(&brcm_global_isp_lock);
brcm_global_isp_in_use--;
mutex_unlock(&brcm_global_isp_lock);
kfree(dev);
return 0;
}
/*
* unicam_disable_clocks - Disable unicam clocks
* @unicam: KONA Unicam device
*/
static void unicam_disable_clocks(struct unicam_device *unicam)
{
int r;
clk_disable(unicam->csi2_axi_clk);
r = pi_mgr_dfs_request_update(&unicam->dfs_client,
PI_MGR_DFS_MIN_VALUE);
if (r)
dev_err(unicam->dev, "failed to update dfs request(min)\n");
}
static int unicam_open(struct inode *inode, struct file *filp)
{
int ret = 0;
struct unicam *dev = kzalloc(sizeof(struct unicam), GFP_KERNEL);
if (!dev)
return -ENOMEM;
filp->private_data = dev;
init_completion(&dev->irq_sem);
dev->irq_pending = 0;
dev->irq_start = 0;
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO)) {
dev_err(unicam_info.dev, "%s:failed to update dfs request for unicam\n",
__func__);
return -EIO;
}
pi_mgr_qos_request_update(&unicam_qos_node, 0);
scu_standby(0);
enable_unicam_clock();
reset_unicam();
unicam_init_camera_intf();
ret =
request_irq(IRQ_UNICAM, unicam_isr, IRQF_DISABLED | IRQF_SHARED,
UNICAM_DEV_NAME, dev);
if (ret) {
dev_err(unicam_info.dev, "%s: request_irq failed ret = %d\n",
__func__, ret);
goto err;
}
if (unicam_info.reg) {
ret = regulator_enable(unicam_info.reg);
if (ret < 0) {
dev_err(unicam_info.dev,
"%s: cannot enable regulator: %d\n",
__func__, ret);
goto err;
}
}
return 0;
err:
kfree(dev);
return ret;
}
static void audio_late_resume(struct early_suspend *s)
{
aTrace(LOG_ALSA_INTERFACE,"audio late resume entered %s", __func__);
if (dfs_node_created && during_playback)
{
int err = 0;
err = pi_mgr_dfs_request_update(&dfs_node, PI_PROC_OPP_NORMAL);
/* Check if the request was handled or not */
if (err) {
aWarn("%s : Warning: could not change the CPU clock to PI_PROC_OPP_NORMAL\n", __func__);
}
}
return;
}
int brcm_enable_dsi_lcd_clocks(
struct pi_mgr_dfs_node* dfs_node,
unsigned int dsi_bus,
unsigned int dsi_pll_hz,
unsigned int dsi_pll_ch_div,
unsigned int esc_clk_hz )
{
struct clk *mm_dma_axi;
struct clk *dsi_axi;
struct clk *dsi_esc;
if (pi_mgr_dfs_request_update(dfs_node, PI_OPP_TURBO))
{
printk(KERN_ERR "Failed to update dfs request for DSI LCD\n");
return -EIO;
}
mm_dma_axi = clk_get (NULL, "mm_dma_axi_clk");
dsi_axi = clk_get (NULL, dsi_bus_clk[dsi_bus].dsi_axi);
dsi_esc = clk_get (NULL, dsi_bus_clk[dsi_bus].dsi_esc);
BUG_ON (!mm_dma_axi || !dsi_axi || !dsi_esc);
if (clk_enable(mm_dma_axi)) {
printk(KERN_ERR "Failed to enable the MM DMA bus clock\n");
return -EIO;
}
if (clk_enable (dsi_axi)) {
printk(KERN_ERR "Failed to enable the DSI[%d] AXI clock\n",
dsi_bus);
return -EIO;
}
if (clk_set_rate(dsi_esc, esc_clk_hz)) {
printk(KERN_ERR "Failed to set the DSI[%d] ESC clk to %d Hz\n",
dsi_bus, esc_clk_hz);
return -EIO;
}
if (clk_enable(dsi_esc)) {
printk(KERN_ERR "Failed to enable the DSI[%d] ESC clk\n",
dsi_bus );
return -EIO;
}
return 0;
}
static int h264_release(struct inode *inode, struct file *filp)
{
struct h264_t *dev = (struct h264_t *) filp->private_data;
/*
Restore the default QOS value.
Restore the minimum value for DVFS
Removes the request for DFS and QOS
Disables the clock.
*/
#ifdef H264_CLK_MGMT
#ifdef H264_QOS_MGMT
pi_mgr_qos_request_update(&h264_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
scu_standby(1);
#endif
disable_h264_clock();
if (pi_mgr_dfs_request_update(&h264_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk(KERN_ERR "%s: failed to update dfs request for h264\n",
__func__);
}
pi_mgr_dfs_request_remove(&h264_dfs_node);
h264_dfs_node.name = NULL;
#ifdef H264_QOS_MGMT
pi_mgr_qos_request_remove(&h264_qos_node);
h264_qos_node.name = NULL;
#endif
#endif
#ifdef ENABLE_H264_INT
free_irq(H264_AOB_IRQ, dev);
free_irq(H264_CME_IRQ, dev);
free_irq(H264_MCIN_CBC_IRQ, dev);
#endif
kfree(dev);
mutex_unlock(&h264_mutex);
return 0;
}
static int isp2_release(struct inode *inode, struct file *filp)
{
struct isp2_t *dev = (struct isp2_t *) filp->private_data;
pi_mgr_qos_request_update(&isp2_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
disable_isp2_clock();
if (pi_mgr_dfs_request_update(&isp2_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk(KERN_ERR "%s: failed to update dfs request for isp2\n",
__func__);
}
pi_mgr_dfs_request_remove(&isp2_dfs_node);
isp2_dfs_node.name = NULL;
pi_mgr_qos_request_remove(&isp2_qos_node);
isp2_qos_node.name = NULL;
free_irq(IRQ_ISP2, dev);
kfree(dev);
return 0;
}
int brcm_disable_smi_lcd_clocks(struct pi_mgr_dfs_node* dfs_node)
{
#ifndef CONFIG_MACH_BCM_FPGA
struct clk *smi_axi;
struct clk *smi;
smi_axi = clk_get (NULL, "smi_axi_clk");
smi = clk_get (NULL, "smi_clk");
BUG_ON(IS_ERR_OR_NULL(smi_axi) || IS_ERR_OR_NULL(smi));
clk_disable(smi);
clk_disable(smi_axi);
if (pi_mgr_dfs_request_update(dfs_node, PI_MGR_DFS_MIN_VALUE))
{
printk(KERN_ERR "Failed to update dfs request for SMI LCD at disable\n");
return -EIO;
}
#endif
return 0;
}
int brcm_enable_smi_lcd_clocks(struct pi_mgr_dfs_node *dfs_node)
{
struct clk *smi_axi;
struct clk *mm_dma_axi;
struct clk *smi;
if (pi_mgr_dfs_request_update(dfs_node, PI_OPP_TURBO))
{
printk(KERN_ERR "Failed to update dfs request for SMI LCD at enable\n");
return -EIO;
}
smi_axi = clk_get (NULL, "smi_axi_clk");
mm_dma_axi = clk_get(NULL, "mm_dma_axi_clk");
smi = clk_get (NULL, "smi_clk");
BUG_ON (!smi_axi || !smi || !mm_dma_axi);
if (clk_set_rate(smi, 250000000)) {
printk(KERN_ERR "Failed to set the SMI peri clock to 250MHZ");
return -EIO;
}
if (clk_enable(smi)) {
printk(KERN_ERR "Failed to enable the SMI peri clock");
return -EIO;
}
if (clk_enable (smi_axi)) {
printk(KERN_ERR "Failed to enable the SMI bus clock");
return -EIO;
}
if (clk_enable(mm_dma_axi)) {
printk(KERN_ERR "Failed to enable the MM DMA bus clock");
return -EIO;
}
return 0;
}
int brcm_disable_smi_lcd_clocks(struct pi_mgr_dfs_node* dfs_node)
{
struct clk *smi_axi;
struct clk *mm_dma_axi;
struct clk *smi;
smi_axi = clk_get (NULL, "smi_axi_clk");
mm_dma_axi = clk_get (NULL, "mm_dma_axi_clk");
smi = clk_get (NULL, "smi_clk");
BUG_ON (!smi_axi || !smi || !mm_dma_axi);
clk_disable(smi);
clk_disable(smi_axi);
clk_disable(mm_dma_axi);
if (pi_mgr_dfs_request_update(dfs_node, PI_MGR_DFS_MIN_VALUE))
{
printk(KERN_ERR "Failed to update dfs request for SMI LCD at disable\n");
return -EIO;
}
return 0;
}
static int enable_h264_clock(void)
{
unsigned long rate;
int ret;
h264_clk = clk_get(NULL, "h264_axi_clk");
if (IS_ERR_OR_NULL(h264_clk)) {
printk("%s: error get clock\n", __func__);
return -EIO;
}
if (pi_mgr_dfs_request_update(&h264_dfs_node, PI_OPP_TURBO)) {
printk(KERN_ERR "%s:failed to update dfs request for h264\n",
__func__);
return -1;
}
ret = clk_enable(h264_clk);
if (ret) {
printk(KERN_ERR "%s: error enable H264 clock\n", __func__);
return -EIO;
}
h264_clk_enabled = 1;
rate = clk_get_rate(h264_clk);
printk(KERN_INFO "h264_clk_clk rate %lu\n", rate);
printk(KERN_INFO
"mmclk policy status 08:%08x 0c:%08x 10:%08x 14:%08x 18:%08x" \
"1c:%08x ec0:%08x\n",
reg_read(mmclk_base, 0x08), reg_read(mmclk_base, 0x0c),
reg_read(mmclk_base, 0x10), reg_read(mmclk_base, 0x14),
reg_read(mmclk_base, 0x18), reg_read(mmclk_base, 0x1c),
reg_read(mmclk_base, 0xec0));
return ret;
}
static int unicam_release(struct inode *inode, struct file *filp)
{
struct unicam *dev = filp->private_data;
disable_irq(IRQ_UNICAM);
free_irq(IRQ_UNICAM, dev);
if (unicam_info.reg) {
if (regulator_disable(unicam_info.reg) < 0)
dev_err(unicam_info.dev, "%s: cannot disable regulator\n",
__func__);
}
reset_unicam();
disable_unicam_clock();
pi_mgr_qos_request_update(&unicam_qos_node, PI_MGR_QOS_DEFAULT_VALUE);
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE))
dev_err(unicam_info.dev, "%s: failed to update dfs request for unicam\n",
__func__);
scu_standby(1);
kfree(dev);
return 0;
}
static int hawaii_camera_power(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *lp_clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_RST, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam0Rst")) {
printk(KERN_ERR "Unable to get cam0 RST GPIO\n");
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_PWRDN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "CamPWDN")) {
printk(KERN_ERR "Unable to get cam0 PWDN GPIO\n");
return -1;
}
/*MMC1 VCC */
d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Failed to get d_1v8_mmc1_vcc\n");
d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "Failed to get d_3v0_mmc1_vcc\n");
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Failed to get d_gpsr_cam0_1v8\n");
if (d_lvldo2_cam1_1v8 == NULL) {
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Fd_lvldo2_cam1_1v8 cam\n");
}
}
ret = -1;
lp_clock = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_0 clock\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI0_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(axi_clk);
if (value) {
pr_err(KERN_ERR "Failed to enable axi clock\n");
goto e_clk_axi;
}
value = clk_enable(lp_clock);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock\n");
goto e_clk_lp;
}
value = clk_set_rate(lp_clock, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock\n");
goto e_clk_set_lp;
}
value = clk_enable(clock);
if (value) {
pr_err("Failed to enable sensor 0 clock\n");
goto e_clk_sensor;
}
value = clk_set_rate(clock, SENSOR_0_CLK_FREQ);
if (value) {
pr_err("Failed to set sensor0 clock\n");
goto e_clk_set_sensor;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_RST, 0);
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, 0);
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_RST, 1);
msleep(30);
} else {
gpio_set_value(SENSOR_0_GPIO_RST, 0);
usleep_range(1000, 1100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, 1);
clk_disable(clock);
clk_disable(lp_clock);
clk_disable(axi_clk);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_3v0_mmc1_vcc);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_sensor:
clk_disable(clock);
e_clk_sensor:
e_clk_set_lp:
clk_disable(lp_clock);
e_clk_lp:
clk_disable(axi_clk);
e_clk_axi:
e_clk_pll:
e_clk_get:
return ret;
}
static int hawaii_camera_power(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *prediv_clock;
struct clk *lp_clock;
struct clk *axi_clk;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
struct cameraCfg_s *thisCfg = getCameraCfg(icl->module_name);
if (NULL == thisCfg) {
printk(KERN_ERR "No cfg for [%s]\n", icl->module_name);
return -1;
}
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_RST, GPIOF_DIR_OUT |
(thisCfg->rst_active<<1), "Cam0Rst")) {
printk(KERN_ERR "Unable to get cam0 RST GPIO\n");
return -1;
}
if (gpio_request_one(SENSOR_0_GPIO_PWRDN, GPIOF_DIR_OUT |
(thisCfg->pwdn_active<<1), "Cam0PWDN")) {
printk(KERN_ERR "Unable to get cam0 PWDN GPIO\n");
return -1;
}
#if defined(CONFIG_MACH_JAVA_C_LC1) \
|| defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
if (gpio_request_one(MAIN_CAM_AF_ENABLE, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam0_af_enable")) {
printk(KERN_ERR "Unable to get cam0 af enable GPIO\n");
return -1;
}
if (gpio_request_one(TORCH_EN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "cam0_torch_enable")) {
printk(KERN_ERR "Unable to get cam0 torch enable GPIO\n");
return -1;
}
if (gpio_request_one(FLASH_EN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "cam0_flash_enable")) {
printk(KERN_ERR "Unable to get cam0 torch enable GPIO\n");
return -1;
}
#endif
/*MMC1 VCC */
d_1v8_mmc1_vcc = regulator_get(NULL, icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Failed to get d_1v8_mmc1_vcc\n");
d_3v0_mmc1_vcc = regulator_get(NULL, icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "Failed to get d_3v0_mmc1_vcc\n");
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Failed to get d_gpsr_cam0_1v8\n");
if (d_lvldo2_cam1_1v8 == NULL) {
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Fd_lvldo2_cam1_1v8 cam\n");
}
}
ret = -1;
lp_clock = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
prediv_clock = clk_get(NULL, SENSOR_PREDIV_CLK);
if (IS_ERR_OR_NULL(prediv_clock)) {
printk(KERN_ERR "Unable to get SENSOR_PREDIV_CLK clock\n");
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_0_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_0 clock\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI0_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI0_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(axi_clk);
if (value) {
pr_err(KERN_ERR "Failed to enable axi clock\n");
goto e_clk_axi;
}
value = clk_enable(lp_clock);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock\n");
goto e_clk_lp;
}
value = clk_set_rate(lp_clock, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock\n");
goto e_clk_set_lp;
}
value = clk_enable(prediv_clock);
if (value) {
pr_err("Failed to enable prediv clock\n");
goto e_clk_prediv;
}
value = clk_enable(clock);
if (value) {
pr_err("Failed to enable sensor 0 clock\n");
goto e_clk_sensor;
}
value = clk_set_rate(prediv_clock, thisCfg->prediv_clk);
if (value) {
pr_err("Failed to set prediv clock\n");
goto e_clk_set_prediv;
}
value = clk_set_rate(clock, thisCfg->clk);
if (value) {
pr_err("Failed to set sensor0 clock\n");
goto e_clk_set_sensor;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_RST, thisCfg->rst_active);
usleep_range(10000, 10100);
gpio_set_value(SENSOR_0_GPIO_PWRDN,
thisCfg->pwdn_active ? 0 : 1);
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_RST,
thisCfg->rst_active ? 0 : 1);
msleep(30);
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
#if defined(CONFIG_MACH_JAVA_C_LC1) || defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
set_af_enable(1);
#endif
#ifdef CONFIG_VIDEO_A3907
a3907_enable(1);
#endif
#ifdef CONFIG_VIDEO_DW9714
dw9714_enable(1);
#endif
} else {
#ifdef CONFIG_VIDEO_A3907
a3907_enable(0);
#endif
#ifdef CONFIG_VIDEO_DW9714
dw9714_enable(0);
#endif
#if defined(CONFIG_MACH_JAVA_C_LC1) || defined(CONFIG_MACH_JAVA_C_5609A) \
|| defined(CONFIG_MACH_JAVA_C_5606)
set_af_enable(0);
#endif
usleep_range(5000, 5100);
gpio_set_value(SENSOR_0_GPIO_PWRDN, thisCfg->pwdn_active);
usleep_range(1000, 1100);
gpio_set_value(SENSOR_0_GPIO_RST, thisCfg->rst_active);
clk_disable(prediv_clock);
clk_disable(clock);
clk_disable(lp_clock);
clk_disable(axi_clk);
regulator_disable(d_3v0_mmc1_vcc);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_sensor:
clk_disable(clock);
e_clk_sensor:
e_clk_set_prediv:
clk_disable(prediv_clock);
e_clk_prediv:
e_clk_set_lp:
clk_disable(lp_clock);
e_clk_lp:
clk_disable(axi_clk);
e_clk_axi:
e_clk_pll:
e_clk_get:
return ret;
}
/*+++++++++++++++++++++++++++++++++++++++++++++++++++++
*
* Function Name: PcmPlaybackTrigger
*
* Description: Command handling function
*
*------------------------------------------------------------
*/
static int PcmPlaybackTrigger(struct snd_pcm_substream *substream, int cmd)
{
int ret = 0;
brcm_alsa_chip_t *chip = snd_pcm_substream_chip(substream);
AUDIO_DRIVER_HANDLE_t drv_handle;
int substream_number = substream->number;
s32 *pSel;
int i, count = 0;
aTrace(LOG_ALSA_INTERFACE,
"ALSA-CAPH PcmPlaybackTrigger stream=%d, cmd %d, start_threshold %ld\n",
substream_number, cmd, substream->runtime->start_threshold);
callMode = chip->iCallMode;
drv_handle = substream->runtime->private_data;
pSel = chip->streamCtl[substream_number].iLineSelect;
for (i = 0; i < MAX_PLAYBACK_DEV; i++) {
chip->streamCtl[substream_number].dev_prop.p[i].source =
AUDIO_SOURCE_MEM;
chip->streamCtl[substream_number].dev_prop.p[i].sink =
AUDIO_SINK_UNDEFINED;
}
if (AUDCTRL_GetMFDMode() &&
(chip->streamCtl[substream_number].iLineSelect[0] ==
AUDIO_SINK_VIBRA)) {
/*With MFD, vibra plays to IHF, and it does not mix with
voice even in call mode */
chip->streamCtl[substream_number].dev_prop.p[0].sink =
AUDIO_SINK_LOUDSPK;
} else if ((callMode == MODEM_CALL)
&& (chip->streamCtl[substream_number].iLineSelect[0]
!= AUDIO_SINK_I2S)) {
/*call mode & not FM Tx playback */
chip->streamCtl[substream_number].dev_prop.p[0].source =
AUDIO_SOURCE_MEM;
chip->streamCtl[substream_number].dev_prop.p[0].sink =
AUDIO_SINK_DSP;
} else {
for (i = 0; i < MAX_PLAYBACK_DEV; i++) {
if (pSel[i] >= AUDIO_SINK_HANDSET
&& pSel[i] < AUDIO_SINK_VALID_TOTAL) {
chip->streamCtl[substream_number].dev_prop.p[i].
sink = pSel[i];
} else {
/* No valid device in the list to do a playback,
* return error
*/
if (++count == MAX_PLAYBACK_DEV) {
aError("No device selected by"
" the user ?\n");
return -EINVAL;
} else
chip->streamCtl[substream_number].
dev_prop.p[i].sink =
AUDIO_SINK_UNDEFINED;
}
}
}
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
{
BRCM_AUDIO_Param_Start_t param_start;
BRCM_AUDIO_Param_Spkr_t param_spkr;
BRCM_AUDIO_Param_Second_Dev_t param_second_spkr;
struct snd_pcm_runtime *runtime = substream->runtime;
if (dfs_node_created)
{
int err = 0;
err = pi_mgr_dfs_request_update(&dfs_node, PI_PROC_OPP_NORMAL);
/* Check if the request was handled or not */
if (err) {
aWarn("%s : Warning: could not change the CPU clock to PI_PROC_OPP_NORMAL\n", __func__);
}
during_playback = TRUE;
}
param_start.drv_handle = drv_handle;
param_start.pdev_prop =
&chip->streamCtl[substream_number].dev_prop;
param_start.channels = runtime->channels;
param_start.rate = runtime->rate;
param_start.vol[0] =
chip->streamCtl[substream_number].ctlLine[pSel[0]].
iVolume[0];
param_start.vol[1] =
chip->streamCtl[substream_number].ctlLine[pSel[0]].
iVolume[1];
param_start.stream = substream_number;
param_second_spkr.source = AUDIO_SOURCE_UNDEFINED;
param_second_spkr.sink = AUDIO_SINK_VALID_TOTAL;
param_second_spkr.pathID = 0;
param_second_spkr.substream_number = substream_number;
/*the for loop starts with p[1], the second channel. */
for (i = 1; i < MAX_PLAYBACK_DEV; i++) {
AUDIO_SINK_Enum_t sink =
chip->streamCtl[substream_number].dev_prop.p[i].sink;
/*to support short tone to stereo IHF + headset,
only care these sinks*/
if (sink == AUDIO_SINK_HEADSET ||
sink == AUDIO_SINK_HEADPHONE ||
sink == AUDIO_SINK_LOUDSPK) {
param_second_spkr.source =
chip->streamCtl[substream_number].
dev_prop.p[i].source;
param_second_spkr.sink =
chip->streamCtl[substream_number].
dev_prop.p[i].sink;
}
}
AUDCTRL_SetSecondSink(param_second_spkr);
AUDIO_Ctrl_Trigger(ACTION_AUD_StartPlay, ¶m_start, NULL, 0);
for (i = 1; i < MAX_PLAYBACK_DEV; i++) {
if (chip->streamCtl[substream_number].dev_prop.
p[i].sink != AUDIO_SINK_UNDEFINED) {
param_spkr.src =
chip->streamCtl[substream_number].
dev_prop.p[i].source;
param_spkr.sink =
chip->streamCtl[substream_number].
dev_prop.p[i].sink;
param_spkr.stream = substream_number;
AUDIO_Ctrl_Trigger
(ACTION_AUD_AddChannel, ¶m_spkr,
NULL, 0);
}
}
}
break;
case SNDRV_PCM_TRIGGER_STOP:
{
BRCM_AUDIO_Param_Stop_t param_stop;
struct completion *compl_ptr;
if (dfs_node_created)
{
int err = 0;
err = pi_mgr_dfs_request_update(&dfs_node, PI_PROC_OPP_ECONOMY1);
/* Check if the request was handled or not */
if (err) {
aWarn("%s : Warning: could not change the CPU clock to PI_PROC_OPP_ECONOMY1\n", __func__);
}
during_playback = FALSE;
}
param_stop.drv_handle = drv_handle;
param_stop.pdev_prop =
&chip->streamCtl[substream_number].dev_prop;
param_stop.stream = substream_number;
aTrace
(LOG_ALSA_INTERFACE,
"ACTION_AUD_StopPlay stream=%d\n",
param_stop.stream);
compl_ptr = &chip->streamCtl[substream_number]
.stopCompletion;
init_completion(compl_ptr);
chip->streamCtl[substream_number].pStopCompletion
= compl_ptr;
AUDIO_Ctrl_Trigger(ACTION_AUD_StopPlay, ¶m_stop,
CtrlStopCB, (int)compl_ptr);
}
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
{
BRCM_AUDIO_Param_Pause_t param_pause;
param_pause.drv_handle = drv_handle;
param_pause.pdev_prop =
&chip->streamCtl[substream_number].dev_prop;
param_pause.stream = substream_number;
AUDIO_Ctrl_Trigger(ACTION_AUD_PausePlay, ¶m_pause,
NULL, 0);
}
break;
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
{
BRCM_AUDIO_Param_Resume_t param_resume;
struct snd_pcm_runtime *runtime = substream->runtime;
param_resume.drv_handle = drv_handle;
param_resume.pdev_prop =
&chip->streamCtl[substream_number].dev_prop;
param_resume.channels = runtime->channels;
param_resume.rate = runtime->rate;
param_resume.stream = substream_number;
AUDIO_Ctrl_Trigger(ACTION_AUD_ResumePlay, ¶m_resume,
NULL, 0);
}
break;
default:
return -EINVAL;
}
return ret;
}
static int hawaii_camera_power_front(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *axi_clk;
struct clk *axi_clk_0;
struct clk *lp_clock_0;
struct clk *lp_clock_1;
static struct pi_mgr_dfs_node unicam_dfs_node;
struct soc_camera_device *icd = to_soc_camera_dev(dev);
struct soc_camera_link *icl = to_soc_camera_link(icd);
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
struct cameraCfg_s *thisCfg = getCameraCfg(icl->module_name);
if (NULL == thisCfg) {
printk(KERN_ERR "No cfg for [%s]\n", icl->module_name);
return -1;
}
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_PWRDN, GPIOF_DIR_OUT |
(thisCfg->pwdn_active<<1), "Cam1PWDN")) {
printk(KERN_ERR "Unable to get CAM1PWDN\n");
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_RST, GPIOF_DIR_OUT |
(thisCfg->rst_active<<1), "Cam1RST")) {
printk(KERN_ERR "Unable to get Cam1RST\n");
return -1;
}
d_lvldo2_cam1_1v8 = regulator_get(NULL,
icl->regulators[0].supply);
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Failed to get d_lvldo2_cam1_1v8\n");
if (d_1v8_mmc1_vcc == NULL) {
d_1v8_mmc1_vcc = regulator_get(NULL,
icl->regulators[1].supply);
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Err d_1v8_mmc1_vcc\n");
}
if (d_3v0_mmc1_vcc == NULL) {
d_3v0_mmc1_vcc = regulator_get(NULL,
icl->regulators[2].supply);
if (IS_ERR_OR_NULL(d_3v0_mmc1_vcc))
printk(KERN_ERR "d_3v0_mmc1_vcc");
}
if (d_gpsr_cam0_1v8 == NULL) {
d_gpsr_cam0_1v8 = regulator_get(NULL,
icl->regulators[3].supply);
if (IS_ERR_OR_NULL(d_gpsr_cam0_1v8))
printk(KERN_ERR "Fl d_gpsr_cam0_1v8 get fail");
}
}
ret = -1;
lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_0)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_1)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI1_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_1_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_1 clock\n");
goto e_clk_get;
}
axi_clk_0 = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk_0)) {
printk(KERN_ERR "Unable to get AXI clock 0\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi1_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock 1\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
gpio_set_value(SENSOR_1_GPIO_PWRDN, thisCfg->pwdn_active);
gpio_set_value(SENSOR_1_GPIO_RST, thisCfg->rst_active);
usleep_range(5000, 5010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
/* Secondary cam addition */
regulator_enable(d_gpsr_cam0_1v8);
usleep_range(1000, 1010);
regulator_enable(d_3v0_mmc1_vcc);
usleep_range(1000, 1010);
gpio_set_value(SENSOR_1_GPIO_RST,
thisCfg->rst_active ? 0 : 1);
if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(lp_clock_0);
if (value) {
printk(KERN_ERR "Failed to enable lp clock 0\n");
goto e_clk_lp0;
}
value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 0\n");
goto e_clk_set_lp0;
}
value = clk_enable(lp_clock_1);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock 1\n");
goto e_clk_lp1;
}
value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 1\n");
goto e_clk_set_lp1;
}
value = clk_enable(axi_clk_0);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 0\n");
goto e_clk_axi_clk_0;
}
value = clk_enable(axi_clk);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 1\n");
goto e_clk_axi;
}
value = clk_enable(clock);
if (value) {
printk("Failed to enable sensor 1 clock\n");
goto e_clk_clock;
}
value = clk_set_rate(clock, thisCfg->clk);
if (value) {
printk("Failed to set sensor 1 clock\n");
goto e_clk_set_clock;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_1_GPIO_PWRDN,
thisCfg->pwdn_active ? 0 : 1);
msleep(30);
} else {
gpio_set_value(SENSOR_1_GPIO_PWRDN, thisCfg->pwdn_active);
usleep_range(1000, 1010);
gpio_set_value(SENSOR_1_GPIO_RST, thisCfg->rst_active);
clk_disable(lp_clock_0);
clk_disable(lp_clock_1);
clk_disable(clock);
clk_disable(axi_clk);
clk_disable(axi_clk_0);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
regulator_disable(d_gpsr_cam0_1v8);
regulator_disable(d_3v0_mmc1_vcc);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_clock:
clk_disable(clock);
e_clk_clock:
clk_disable(axi_clk);
e_clk_axi:
clk_disable(axi_clk_0);
e_clk_axi_clk_0:
e_clk_set_lp1:
clk_disable(lp_clock_1);
e_clk_lp1:
e_clk_set_lp0:
clk_disable(lp_clock_0);
e_clk_lp0:
e_clk_pll:
e_clk_get:
return ret;
}
static int hawaii_camera_power_front(struct device *dev, int on)
{
unsigned int value;
int ret = -1;
struct clk *clock;
struct clk *axi_clk;
struct clk *axi_clk_0;
struct clk *lp_clock_0;
struct clk *lp_clock_1;
static struct pi_mgr_dfs_node unicam_dfs_node;
printk(KERN_INFO "%s:camera power %s\n", __func__, (on ? "on" : "off"));
if (!unicam_dfs_node.valid) {
ret = pi_mgr_dfs_add_request(&unicam_dfs_node, "unicam",
PI_MGR_PI_ID_MM,
PI_MGR_DFS_MIN_VALUE);
if (ret) {
return -1;
}
if (gpio_request_one(SENSOR_1_GPIO_PWRDN, GPIOF_DIR_OUT |
GPIOF_INIT_LOW, "Cam1PWDN")) {
printk(KERN_ERR "Unable to get CAM1PWDN\n");
return -1;
}
d_lvldo2_cam1_1v8 = regulator_get(NULL, "lvldo2_uc");
if (IS_ERR_OR_NULL(d_lvldo2_cam1_1v8))
printk(KERN_ERR "Failed to get d_lvldo2_cam1_1v8\n");
if (d_1v8_mmc1_vcc == NULL) {
d_1v8_mmc1_vcc = regulator_get(NULL, "mmc1_vcc");
if (IS_ERR_OR_NULL(d_1v8_mmc1_vcc))
printk(KERN_ERR "Err d_1v8_mmc1_vcc\n");
}
}
ret = -1;
lp_clock_0 = clk_get(NULL, CSI0_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_0)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI0_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
lp_clock_1 = clk_get(NULL, CSI1_LP_PERI_CLK_NAME_STR);
if (IS_ERR_OR_NULL(lp_clock_1)) {
printk(KERN_ERR "Unable to get %s clock\n",
CSI1_LP_PERI_CLK_NAME_STR);
goto e_clk_get;
}
clock = clk_get(NULL, SENSOR_1_CLK);
if (IS_ERR_OR_NULL(clock)) {
printk(KERN_ERR "Unable to get SENSOR_1 clock\n");
goto e_clk_get;
}
axi_clk_0 = clk_get(NULL, "csi0_axi_clk");
if (IS_ERR_OR_NULL(axi_clk_0)) {
printk(KERN_ERR "Unable to get AXI clock 0\n");
goto e_clk_get;
}
axi_clk = clk_get(NULL, "csi1_axi_clk");
if (IS_ERR_OR_NULL(axi_clk)) {
printk(KERN_ERR "Unable to get AXI clock 1\n");
goto e_clk_get;
}
if (on) {
if (pi_mgr_dfs_request_update(&unicam_dfs_node, PI_OPP_TURBO))
printk("DVFS for UNICAM failed\n");
gpio_set_value(SENSOR_1_GPIO_PWRDN, 1);
usleep_range(5000, 5010);
regulator_enable(d_lvldo2_cam1_1v8);
usleep_range(1000, 1010);
regulator_enable(d_1v8_mmc1_vcc);
usleep_range(1000, 1010);
if (mm_ccu_set_pll_select(CSI1_BYTE1_PLL, 8)) {
pr_err("failed to set BYTE1\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_BYTE0_PLL, 8)) {
pr_err("failed to set BYTE0\n");
goto e_clk_pll;
}
if (mm_ccu_set_pll_select(CSI1_CAMPIX_PLL, 8)) {
pr_err("failed to set PIXPLL\n");
goto e_clk_pll;
}
value = clk_enable(lp_clock_0);
if (value) {
printk(KERN_ERR "Failed to enable lp clock 0\n");
goto e_clk_lp0;
}
value = clk_set_rate(lp_clock_0, CSI0_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 0\n");
goto e_clk_set_lp0;
}
value = clk_enable(lp_clock_1);
if (value) {
pr_err(KERN_ERR "Failed to enable lp clock 1\n");
goto e_clk_lp1;
}
value = clk_set_rate(lp_clock_1, CSI1_LP_FREQ);
if (value) {
pr_err("Failed to set lp clock 1\n");
goto e_clk_set_lp1;
}
value = clk_enable(axi_clk_0);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 0\n");
goto e_clk_axi_clk_0;
}
value = clk_enable(axi_clk);
if (value) {
printk(KERN_ERR "Failed to enable axi clock 1\n");
goto e_clk_axi;
}
value = clk_enable(clock);
if (value) {
printk("Failed to enable sensor 1 clock\n");
goto e_clk_clock;
}
value = clk_set_rate(clock, SENSOR_1_CLK_FREQ);
if (value) {
printk("Failed to set sensor 1 clock\n");
goto e_clk_set_clock;
}
usleep_range(10000, 10100);
gpio_set_value(SENSOR_1_GPIO_PWRDN, 0);
msleep(30);
} else {
gpio_set_value(SENSOR_1_GPIO_PWRDN, 1);
clk_disable(lp_clock_0);
clk_disable(lp_clock_1);
clk_disable(clock);
clk_disable(axi_clk);
clk_disable(axi_clk_0);
regulator_disable(d_lvldo2_cam1_1v8);
regulator_disable(d_1v8_mmc1_vcc);
if (pi_mgr_dfs_request_update
(&unicam_dfs_node, PI_MGR_DFS_MIN_VALUE)) {
printk("Failed to set DVFS for unicam\n");
}
}
return 0;
e_clk_set_clock:
clk_disable(clock);
e_clk_clock:
clk_disable(axi_clk);
e_clk_axi:
clk_disable(axi_clk_0);
e_clk_axi_clk_0:
e_clk_set_lp1:
clk_disable(lp_clock_1);
e_clk_lp1:
e_clk_set_lp0:
clk_disable(lp_clock_0);
e_clk_lp0:
e_clk_pll:
e_clk_get:
return ret;
}
