struct pic_ops *
setup_iocc(void)
{
struct pic_ops *pic;
int i;
pic = malloc(sizeof(struct pic_ops), M_DEVBUF, M_NOWAIT);
KASSERT(pic != NULL);
pic->pic_numintrs = 16;
pic->pic_cookie = (void *)NULL;
pic->pic_enable_irq = iocc_enable_irq;
pic->pic_reenable_irq = iocc_enable_irq;
pic->pic_disable_irq = iocc_disable_irq;
pic->pic_get_irq = iocc_get_irq;
pic->pic_ack_irq = iocc_ack_irq;
pic->pic_establish_irq = dummy_pic_establish_intr;
pic->pic_finish_setup = NULL;
strcpy(pic->pic_name, "iocc");
pic_add(pic);
/* set all priorities as high */
for (i=0; i < pic->pic_numintrs; i++)
iocc_set_priority(0, 0, i);
return(pic);
}
void
discoverypic_setup(bus_space_tag_t memt, bus_space_handle_t memh)
{
struct discoverypic_ops *dsc;
uint32_t val;
dsc = malloc(sizeof(*dsc), M_DEVBUF, M_NOWAIT|M_ZERO);
if (!dsc)
panic("dsc_pic_setup: malloc(%zu) failed", sizeof(*dsc));
dsc->dsc_memt = memt;
dsc->dsc_memh = memh;
dsc->dsc_pic.pic_get_irq = dsc_get_irq;
dsc->dsc_pic.pic_enable_irq = dsc_enable_irq;
dsc->dsc_pic.pic_reenable_irq = dsc_enable_irq;
dsc->dsc_pic.pic_disable_irq = dsc_disable_irq;
dsc->dsc_pic.pic_ack_irq = dsc_ack_irq;
dsc->dsc_pic.pic_establish_irq = dsc_establish_irq;
dsc->dsc_pic.pic_source_name = dsc_source_name;
pic_add(&dsc->dsc_pic);
KASSERT(dsc->dsc_pic.pic_intrbase == 0);
pic = dscpic_setup(memt, memh);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP7_0,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP15_8,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP23_16,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
intr_establish(dsc->dsc_pic.pic_intrbase + IRQ_GPP31_24,
IST_LEVEL, IPL_NONE, pic_handle_intr, pic);
}
static struct pic_ops *
gpp_pic_setup(bus_space_tag_t memt, bus_space_handle_t memh)
{
struct gpppic_ops * gpp;
uint32_t val;
gpp = malloc(sizeof(*gpp), M_DEVBUF, M_NOWAIT|M_ZERO);
if (!gpp)
panic("gpp_pic_setup: malloc(%zu) failed", sizeof(*gpp));
gpp->gpp_memt = memt;
gpp->gpp_memh = memh;
gpp->gpp_pic.pic_get_irq = gpp_get_irq;
gpp->gpp_pic.pic_enable_irq = gpp_enable_irq;
gpp->gpp_pic.pic_reenable_irq = gpp_enable_irq;
gpp->gpp_pic.pic_disable_irq = gpp_disable_irq;
gpp->gpp_pic.pic_ack_irq = gpp_ack_irq;
gpp->gpp_pic.pic_establish_irq = gpp_establish_irq;
gpp->gpp_pic.pic_source_name = gpp_source_name;
/*
* Force GPP interrupts to be level sensitive.
*/
val = bus_space_read_4(&gpp->gpp_memt, gpp->gpp_memh, 0xf300);
bus_space_write_4(&gpp->gpp_memt, gpp->gpp_memh, 0xf300, val | 0x400);
pic_add(&gpp->gpp_pic);
return &gpp->gpp_pic;
}
struct pic_ops *
setup_prepivr(int ivrtype)
{
struct i8259_ops *prepivr;
struct pic_ops *pic;
uint32_t pivr;
prepivr = kmem_alloc(sizeof(*prepivr), KM_SLEEP);
KASSERT(prepivr != NULL);
pic = &prepivr->pic;
pivr = prep_intr_reg + prep_intr_reg_off;
pic->pic_numintrs = 16;
pic->pic_cookie = (void *)pivr;
pic->pic_enable_irq = i8259_enable_irq;
pic->pic_reenable_irq = i8259_enable_irq;
pic->pic_disable_irq = i8259_disable_irq;
if (ivrtype == PIC_IVR_MOT)
pic->pic_get_irq = motivr_get_irq;
else
pic->pic_get_irq = prepivr_get_irq;
pic->pic_ack_irq = i8259_ack_irq;
pic->pic_establish_irq = prepivr_establish_irq;
pic->pic_finish_setup = NULL;
strcpy(pic->pic_name, "prepivr");
pic_add(pic);
prepivr->pending_events = 0;
prepivr->enable_mask = 0xffffffff;
prepivr->irqs = 0;
/* initialize the ELCR */
isa_outb(IO_ELCR1, (0 >> 0) & 0xff);
isa_outb(IO_ELCR2, (0 >> 8) & 0xff);
i8259_initialize();
return pic;
}
