/******************************************************************************* * Perform any BL31 platform setup common to ARM standard platforms ******************************************************************************/ void arm_bl31_platform_setup(void) { /* Initialize the GIC driver, cpu and distributor interfaces */ plat_arm_gic_driver_init(); plat_arm_gic_init(); #if RESET_TO_BL31 /* * Do initial security configuration to allow DRAM/device access * (if earlier BL has not already done so). */ plat_arm_security_setup(); #endif /* RESET_TO_BL31 */ /* Enable and initialize the System level generic timer */ mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); /* Allow access to the System counter timer module */ arm_configure_sys_timer(); /* Initialize power controller before setting up topology */ plat_arm_pwrc_setup(); }
void bl31_platform_setup(void) { /* Initialize the gic cpu and distributor interfaces */ plat_arm_gic_driver_init(); plat_arm_gic_init(); zynqmp_testing_setup(); }
/******************************************************************************* * Perform any BL3-1 platform setup code ******************************************************************************/ void bl31_platform_setup(void) { platform_setup_cpu(); platform_setup_sram(); generic_delay_timer_init(); /* Initialize the gic cpu and distributor interfaces */ plat_arm_gic_driver_init(); plat_arm_gic_init(); #if ENABLE_PLAT_COMPAT /* Topologies are best known to the platform. */ mt_setup_topology(); #endif /* Initialize spm at boot time */ spm_boot_init(); }
static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) { unsigned int cpu_id = plat_my_core_pos(); const struct pm_proc *proc = pm_get_proc(cpu_id); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); /* Clear the APU power control register for this cpu */ pm_client_wakeup(proc); /* enable coherency */ plat_arm_interconnect_enter_coherency(); /* APU was turned off */ if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { plat_arm_gic_init(); } else { gicv2_cpuif_enable(); gicv2_pcpu_distif_init(); } }
/******************************************************************************* * Perform platform specific setup placeholder ******************************************************************************/ void tsp_platform_setup(void) { plat_arm_gic_driver_init(); plat_arm_gic_init(); }