void init_platform()
{
	platform_setup_timer();
	platform_setup_interrupts();

	return;
}
void platform_setup_interrupts()
{
    XIntc *intcp;
    intcp = &intc;

    XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
    XIntc_Start(intcp, XIN_REAL_MODE);


    platform_setup_timer();

    /*
     * Initialize the exception table.
     */
    Xil_ExceptionInit();

    /*
     * Register the interrupt controller handler with the exception table.
     */
    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
                                 (Xil_ExceptionHandler) XIntc_InterruptHandler,
                                 intcp);


#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
    /* Enable timer and EMAC interrupts in the interrupt controller */
    XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
                     PLATFORM_TIMER_INTERRUPT_MASK |
#endif
                     XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif



#ifdef XPAR_INTC_0_LLTEMAC_0_VEC_ID
#ifdef __MICROBLAZE__
    XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
    XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);
#endif


#ifdef XPAR_INTC_0_AXIETHERNET_0_VEC_ID
    XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
    XIntc_Enable(intcp, XPAR_INTC_0_AXIETHERNET_0_VEC_ID);
#endif


#ifdef XPAR_INTC_0_EMACLITE_0_VEC_ID
#ifdef __MICROBLAZE__
    XIntc_Enable(intcp, PLATFORM_TIMER_INTERRUPT_INTR);
#endif
    XIntc_Enable(intcp, XPAR_INTC_0_EMACLITE_0_VEC_ID);
#endif




}
Exemple #3
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void platform_setup_interrupts()
{
	XIntc *intcp;
	intcp = &intc;

	XIntc_Initialize(intcp, XPAR_XPS_INTC_0_DEVICE_ID);
	XIntc_Start(intcp, XIN_REAL_MODE);

	/* Start the interrupt controller */
	XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR);

#ifdef __PPC__
	Xil_ExceptionInit();
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
			(XExceptionHandler)XIntc_DeviceInterruptHandler,
			(void*) XPAR_XPS_INTC_0_DEVICE_ID);
#elif __MICROBLAZE__
	microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
#endif

	platform_setup_timer();

#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
	/* Enable timer and EMAC interrupts in the interrupt controller */
	XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
			PLATFORM_TIMER_INTERRUPT_MASK |
#endif
			XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif
}