/*============================================================================*/ bool usb_handshake(struct bldr_command_handler *handler) { uint32 enum_tmo = CFG_USB_ENUM_TIMEOUT_EN ? USB_ENUM_TIMEOUT : 0; uint32 handshake_tmo = CFG_USB_HANDSHAKE_TIMEOUT_EN ? USB_SYNC_TIME : 0; bool result = FALSE; bool force_download = FALSE; platform_vusb_on(); force_download = platform_com_wait_forever_check(); if (TRUE == force_download) { enum_tmo = 0; handshake_tmo = 0; } else if (!usb_cable_in()) { return FALSE; } print("%s USB enum timeout (%s), handshake timeout(%s)\n", MOD, enum_tmo ? "Yes" : "No", handshake_tmo ? "Yes" : "No"); usbdl_init(); udelay(1000); usb_disconnect(); if (usb_connect(enum_tmo) == FALSE) { print("%s USB enum timeout!\n", MOD); goto end; } udelay(1000); if (FALSE == usb_handshake_handler(handler, handshake_tmo)) { goto end; } result = TRUE; if (FALSE == usb_port_down(USB_PORT_DOWN_TIME)) { print("%s USB port down timeout!\n", MOD); } end: usb_service_offline(); #if CFG_USBIF_COMPLIANCE /* USB compliance test: 100mA charging current when USB is unconfigured. */ platform_set_chrg_cur(70); #endif return result; }
void platform_pre_init(void) { u32 ret; u32 pmic_ret; u32 pwrap_ret,i; #ifdef PL_PROFILING u32 profiling_time; profiling_time = 0; #endif pwrap_ret = 0; i = 0; ret = 0; /* init timer */ mtk_timer_init(); /* init boot time */ g_boot_time = get_timer(0); #if 0 /* FIXME */ /* * NoteXXX: CPU 1 may not be reset clearly after power-ON. * Need to apply a S/W workaround to manualy reset it first. */ { U32 val; val = DRV_Reg32(0xC0009010); DRV_WriteReg32(0xC0009010, val | 0x2); gpt_busy_wait_us(10); DRV_WriteReg32(0xC0009010, val & ~0x2); gpt_busy_wait_us(10); } #ifndef SLT_BOOTLOADER /* power off cpu1 for power saving */ power_off_cpu1(); #endif #endif ptp_init1(); /* move pll code to audio_sys_ram */ memcpy((char *)&Image$$PLL_INIT$$Base, &__load_start_pll_text, &__load_stop_pll_text - &__load_start_pll_text); /* init pll */ /* for memory preserved mode */ // do not init pll/emi in memory preserved mode, due to code is located in EMI // set all pll except EMI mtk_pll_init(); /*GPIO init*/ #if (!(CFG_FPGA_PLATFORM)) && defined(DUMMY_AP_BOOTLOADER) mt_gpio_set_default(); #endif //set UART1 GPIO to mode1, AP mt_gpio_init_post(0); /* init uart baudrate when pll on */ mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE); /* init pmic i2c interface and pmic */ /* no need in MT6572*/ //i2c_ret = i2c_v1_init(); //retry 3 times for pmic wrapper init #ifdef PL_PROFILING profiling_time = get_timer(0); #endif pwrap_init_preloader(); /* check is uart cable in*/ #if (CFG_USB_UART_SWITCH) platform_vusb_on(); if (is_uart_cable_inserted()) { print("\n%s Switch to UART Mode\n", MOD); mt_usb_set_to_uart_mode(); } else { print("\n%s Keep stay in USB Mode\n", MOD); } #endif if (platform_sram_repair_enable_check()) { //MM SRAM Repair ret = MFG_MM_SRAM_repair(); if (ret < 0 ) printf("MFG_MM_SRAM_repair fail\n"); else printf("MFG_MM_SRAM_repair OK\n"); } #ifdef PL_PROFILING printf("#T#pwrap_init=%d\n", get_timer(profiling_time)); profiling_time = get_timer(0); //for next #endif pmic_ret = pmic_init(); //enable long press reboot function*************** #ifndef CFG_EVB_PLATFORM #ifdef KPD_PMIC_LPRST_TD #ifdef ONEKEY_REBOOT_NORMAL_MODE_PL printf("ONEKEY_REBOOT_NORMAL_MODE_PL OK\n"); pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT);//pmic_config_interface(TOP_RST_MISC, 0x01, PMIC_RG_PWRKEY_RST_EN_MASK, PMIC_RG_PWRKEY_RST_EN_SHIFT); pmic_config_interface(TOP_RST_MISC, (U32)KPD_PMIC_LPRST_TD, PMIC_RG_PWRKEY_RST_TD_MASK, PMIC_RG_PWRKEY_RST_TD_SHIFT); #endif #endif #endif //************************************************ #ifdef PL_PROFILING printf("#T#pmic_init=%d\n", get_timer(profiling_time)); #endif print("%s Init PWRAP: %s(%d)\n", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret); print("%s Init PMIC: %s(%d)\n", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret); print("%s chip[%x]\n", MOD, platform_chip_ver()); }