TVE_STATUS TVE_PowerOn() { if (!s_isTvePowerOn) { BOOL ret; #if 1 ret = pll_fsel(MT65XX_TVDDS, 0x38E40A8E); ASSERT(!ret); ret = enable_pll(MT65XX_TVDDS, "TVE"); ASSERT(!ret); ret = enable_clock(MT65XX_PDN_MM_TVE, "TVE"); ASSERT(!ret); #else ret = enable_clock(MT65XX_PDN_MM_TVE, "TVE"); ASSERT(!ret); //Enable TVDSS, set it to 27MHZ OUTREG32(0xf00071A0,0x0A8E); OUTREG32(0xf00071A4,0x38E4); OUTREG32(0xf00071A8,0x7C54); msleep(10); //waiting for PLL stable #endif _RestoreTVERegisters(); s_isTvePowerOn = TRUE; } return TVE_STATUS_OK; }
void AudDrv_APLL24M_Clk_On(void) { pr_debug("+%s %d \n", __func__, Aud_APLL24M_Clk_cntr); #if !defined(CONFIG_MTK_LEGACY) int ret = 0; #endif mutex_lock(&auddrv_pmic_mutex); if (Aud_APLL24M_Clk_cntr == 0) { PRINTK_AUDDRV("+%s enable_clock ADC clk(%x)\n", __func__, Aud_APLL24M_Clk_cntr); #ifdef PM_MANAGER_API enable_mux(MT_MUX_AUD1, "AUDIO"); clkmux_sel(MT_MUX_AUD1, 1, "AUDIO"); //hf_faud_1_ck apll1_ck pll_fsel(APLL1, 0xbc7ea932); //ALPP1 98.304M #if defined(CONFIG_MTK_LEGACY) if (enable_clock(MT_CG_AUDIO_24M, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } if (enable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } #else if (paudclk->aud_apll24m_clk_status) { ret = clk_prepare_enable(paudclk->aud_apll24m_clk); if (!ret) { pr_err("%s Aud enable_clock enable_clock aud_apll24m_clk fail", __func__); BUG(); return; } } else { pr_err("%s clk_status error Aud enable_clock aud_apll24m_clk fail", __func__); BUG(); return; } if (paudclk->aud_apll2_tuner_clk_status) { ret = clk_prepare_enable(paudclk->aud_apll2_tuner_clk); if (!ret) { pr_err("%s Aud enable_clock enable_clock aud_apll2_tuner_clk fail", __func__); BUG(); return; } } else { pr_err("%s clk_status error Aud enable_clock aud_apll2_tuner_clk fail", __func__); BUG(); return; } #endif #endif } Aud_APLL24M_Clk_cntr++; mutex_unlock(&auddrv_pmic_mutex); }
void AudDrv_APLL22M_Clk_On(void) { pr_debug("+%s %d \n", __func__, Aud_APLL22M_Clk_cntr); #if !defined(CONFIG_MTK_LEGACY) int ret = 0; #endif mutex_lock(&auddrv_pmic_mutex); if (Aud_APLL22M_Clk_cntr == 0) { PRINTK_AUDDRV("+%s enable_clock ADC clk(%x)\n", __func__, Aud_APLL22M_Clk_cntr); #ifdef PM_MANAGER_API pr_debug("+%s enable_mux ADC \n", __func__); enable_mux(MT_MUX_AUD1, "AUDIO");//MT_MUX_AUD1 CLK_CFG_6 => [7]: pdn_aud_1 [15]: ,MT_MUX_AUD2: pdn_aud_2 clkmux_sel(MT_MUX_AUD1, 1 , "AUDIO"); //select APLL1 ,hf_faud_1_ck is mux of 26M and APLL1_CK pll_fsel(APLL1, 0xb7945ea6); //APLL1 90.3168M //pdn_aud_1 => power down hf_faud_1_ck, hf_faud_1_ck is mux of 26M and APLL1_CK //pdn_aud_2 => power down hf_faud_2_ck, hf_faud_2_ck is mux of 26M and APLL2_CK (D1 is WHPLL) #if defined(CONFIG_MTK_LEGACY) if (enable_clock(MT_CG_AUDIO_22M, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } if (enable_clock(MT_CG_AUDIO_APLL_TUNER, "AUDIO")) { PRINTK_AUD_CLK("%s fail", __func__); } #else if (paudclk->aud_apll22m_clk_status) { ret = clk_prepare_enable(paudclk->aud_apll22m_clk); if (!ret) { pr_err("%s Aud enable_clock enable_clock aud_apll22m_clk fail", __func__); BUG(); return; } } else { pr_err("%s clk_status error Aud enable_clock aud_apll22m_clk fail", __func__); BUG(); return; } if (paudclk->aud_apll1_tuner_clk_status) { ret = clk_prepare_enable(paudclk->aud_apll1_tuner_clk); if (!ret) { pr_err("%s Aud enable_clock enable_clock aud_apll1_tuner_clk fail", __func__); BUG(); return; } } else { pr_err("%s clk_status error Aud enable_clock aud_apll1_tuner_clk fail", __func__); BUG(); return; } #endif #endif } Aud_APLL22M_Clk_cntr++; mutex_unlock(&auddrv_pmic_mutex); }