void pm_configure_usb_clock(void)
{
volatile avr32_pm_t *pm = &AVR32_PM;
#if __AVR32_UC3A3256__ || __AVR32_UC3A3128__ || __AVR32_UC3A364__ || \
__AVR32_UC3A3256S__ || __AVR32_UC3A3128S__ || __AVR32_UC3A364S__ || \
__AT32UC3A3256__ || __AT32UC3A3128__ || __AT32UC3A364__ || \
__AT32UC3A3256S__ || __AT32UC3A3128S__ || __AT32UC3A364S__
// Setup USB GCLK.
pm_gc_setup(pm, AVR32_PM_GCLK_USBB, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
#else
// Set PLL1 @ 96 MHz from Osc0: 12MHz*(7+1)/1 = 96MHz.
// In order to work, we need to go above 80MHz, then divide.
pm_pll_setup(pm, 1, // pll
7, // mul
1, // div
0, // osc
16); // lockcount
pm_pll_set_option(pm, 1, // pll1
1, // Choose the range 80-180MHz.
1, // div2
0); // wbwdisable
// Enable PLL1.
pm_pll_enable(pm, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(pm);
// Setup USB GCLK.
pm_gc_setup(pm, AVR32_PM_GCLK_USBB, // gc
1, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
#endif
}
static void init_codec_gclk(void)
{
// Configure the ABDAC generic clock
// We do not activate it here since it is done in the low level DRIVERS/ABDAC/abdac.c driver.
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_ABDAC,
AVR32_GC_USES_OSC, AVR32_GC_USES_OSC1, 0, 0);
}
/* Enable the specified GCLK output on the nominated pin for the selected board. */
static void local_enable_gclk_on_gpio(volatile avr32_pm_t* pm)
{
#if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK ) || ( BOARD == STK600_RCUC3D )
// Note: for UC3L and UC3C devices, the generic clock configurations are handled
// by the SCIF module.
/* setup generic clock on Osc0, no divisor */
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_OSC0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
/* Now enable the generic clock */
scif_gc_enable(EXAMPLE_GCLK_ID);
#else
/* setup generic clock on Osc0, no divisor */
pm_gc_setup(pm, EXAMPLE_GCLK_ID, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, AVR32_GC_NO_DIV_CLOCK, 0);
/* Now enable the generic clock */
pm_gc_enable(pm, EXAMPLE_GCLK_ID);
#endif
/* Assign a GPIO to generic clock output */
gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
// Note that gclk0_1 is GPIO pin 51 pb19 on AT32UC3A0512 QFP144.
// Note that gclk2 is GPIO pin 30 pa30 on AT32UC3B0256 QFP64.
// Note that gclk1 is GPIO pin 43 pb11 on AT32UC3A3256 QFP144.
// Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48.
// Note that gclk0 is GPIO pin 54 pb22 on AT32UC3C0512C QFP144.
// Note that gclk0 is GPIO pin 9 pa03 on ATUC128D3 QFN64.
}
/*! \brief Sets up generic clock for the audio codec.
*/
static void init_codec_gclk(void)
{
// Use PBA for the I2S clock
const int gc = 0;
gpio_enable_module_pin(TLV320_PM_GCLK_PIN, TLV320_PM_GCLK_FUNCTION);
pm_gc_setup(&AVR32_PM, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 0, 0);
pm_gc_enable(&AVR32_PM, gc);
}
/*! \brief Sets up generic clock for the audio codec.
*/
static void init_codec_gclk(void)
{
#if defined(AIC23B_DAC_USE_RX_CLOCK) && AIC23B_DAC_USE_RX_CLOCK == ENABLED
// GCLK to supply the I2S TX clock
gpio_enable_module_pin(TLV320_PM_GCLK_RX_PIN, TLV320_PM_GCLK_RX_FUNCTION);
gpio_enable_module_pin(TLV320_PM_GCLK_PIN, TLV320_PM_GCLK_FUNCTION);
#else
// Use PBA for the I2S clock
const int gc = 0;
gpio_enable_module_pin(TLV320_PM_GCLK_PIN, TLV320_PM_GCLK_FUNCTION);
#if AIC23B_MCLK_HZ == 11289600
pm_gc_setup(&AVR32_PM, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC1, 0, 0);
#elif AIC23B_MCLK_HZ == 12000000
pm_gc_setup(&AVR32_PM, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 0, 0);
#endif
pm_gc_enable(&AVR32_PM, gc);
#endif
}
void pm_configure_usb_clock(void)
{
#if (defined __AVR32_UC3A3256__) || (defined __AVR32_UC3A3128__) || (defined __AVR32_UC3A364__) || \
(defined __AVR32_UC3A3256S__) || (defined __AVR32_UC3A3128S__) || (defined __AVR32_UC3A364S__) || \
(defined __AT32UC3A3256__) || (defined __AT32UC3A3128__) || (defined __AT32UC3A364__) || \
(defined __AT32UC3A3256S__) || (defined __AT32UC3A3128S__) || (defined __AT32UC3A364S__)
// Setup USB GCLK.
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven
0); // div
// Enable USB GCLK.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#else
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
#endif
}
void set_gclk2_freq(int freq_hz)
{
const int gc_master_clock = 0;
const int gc_tx_clock = 2;
int temp;
pm_gc_disable(&AVR32_PM, gc_master_clock);
pm_gc_disable(&AVR32_PM, gc_tx_clock);
switch (freq_hz)
{
// 32000 - stereo - 16 bits -> PLL0 (62.092MHz)
case (32000*2*16):
// Codec master clock - 12MHz
pm_gc_setup(&AVR32_PM, gc_master_clock, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 0, 0);
// I2S TX clock - 48MHz/46 ~ 1.024MHz = freq_hz
pm_gc_setup(&AVR32_PM, gc_tx_clock, AVR32_GC_USES_PLL, AVR32_GC_USES_PLL1, 1, 22);
// Configure the DAC
aic23b_configure_freq(FOSC0, 32000);
break;
// 44100 - stereo - 16 bits -> OSC1 (11.289600MHz)
case (44100*2*16):
// Codec master clock - 11.289600MHz
pm_gc_setup(&AVR32_PM, gc_master_clock, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC1, 0, 0);
// I2S TX clock - 11.289600MHz/8 = 1.4112MHz = freq_hz
pm_gc_setup(&AVR32_PM, gc_tx_clock, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC1, 1, 3);
// Configure the DAC
aic23b_configure_freq(FOSC1, 44100);
break;
// 48000 - stereo - 16 bits -> PLL1 (48MHz)
case (48000*2*16):
// Codec master clock - 12MHz
pm_gc_setup(&AVR32_PM, gc_master_clock, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 0, 0);
// I2S TX clock - 48MHz/32 ~ 1.536MHz = freq_hz
pm_gc_setup(&AVR32_PM, gc_tx_clock, AVR32_GC_USES_PLL, AVR32_GC_USES_PLL1, 1, 15);
// Configure the DAC
aic23b_configure_freq(FOSC0, 48000);
break;
default:
// not supported! (but we try anyway! to avoid locked-up conditions)
// Codec master clock - 12MHz
pm_gc_setup(&AVR32_PM, gc_master_clock, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 0, 0);
// I2S TX clock
temp = (FOSC0 + freq_hz) / (2*freq_hz) - 1;
pm_gc_setup(&AVR32_PM, gc_tx_clock, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 1, temp);
// Configure the DAC
aic23b_configure_freq(FOSC0, freq_hz / (2*16));
}
pm_gc_enable(&AVR32_PM, gc_tx_clock);
pm_gc_enable(&AVR32_PM, gc_master_clock);
}
/*! \brief Sets up generic clock for the audio codec.
*/
static void init_codec_gclk(void)
{
#if(DEFAULT_DACS == AUDIO_MIXER_DAC_ABDAC)
// Configure the ABDAC generic clock
// We do not activate it here since this is done by activating the
// ABDAC in the driver.
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_ABDAC,
AVR32_GC_USES_OSC, AVR32_GC_USES_OSC1, 0, 0);
#elif(DEFAULT_DACS == AUDIO_MIXER_DAC_AIC23B)
int gc = 0;
gpio_enable_module_pin(TLV320_PM_GCLK_PIN, TLV320_PM_GCLK_FUNCTION);
# if(AIC23B_MCLK_HZ == 11289600)
pm_gc_setup(&AVR32_PM, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC1, 0, 0);
# elif(AIC23B_MCLK_HZ == 12000000)
pm_gc_setup(&AVR32_PM, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, 0, 0);
# else
# error Wrong Master clock configuration
# endif
pm_gc_enable(&AVR32_PM, gc);
#endif
}
/* \brief Set-up a generic clock to run from a high-frequency clock and output it to a gpio pin.
*
*/
static void local_start_gc(void)
{
#if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
// Note: for UC3L devices, the generic clock configurations are handled by the
// SCIF module.
// Setup gc to use the DFLL0 as source clock, divisor enabled, apply a division factor.
// Since the DFLL0 frequency is 96MHz, set the division factor to 2 to have a
// gclk frequency of 48MHz.
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 2);
/* Now enable the generic clock */
scif_gc_enable(EXAMPLE_GCLK_ID);
#elif BOARD == UC3C_EK || BOARD == STK600_RCUC3D
// Note: for UC3 C, D and L series, the generic clock configurations are handled by the
// SCIF module.
/* setup gc on Osc0, no divisor */
scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_PLL0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
/* Now enable the generic clock */
scif_gc_enable(EXAMPLE_GCLK_ID);
#else
volatile avr32_pm_t* pm = &AVR32_PM;
/* Setup generic clock on PLL0, with Osc0/PLL0, no divisor */
/*
void pm_gc_setup(volatile avr32_pm_t* pm,
unsigned int gc,
unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
unsigned int diven,
unsigned int div) {
*/
pm_gc_setup(pm,
EXAMPLE_GCLK_ID,
1, // Use Osc (=0) or PLL (=1), here PLL
0, // Sel Osc0/PLL0 or Osc1/PLL1
0, // disable divisor
0); // no divisor
/* Enable Generic clock */
pm_gc_enable(pm, EXAMPLE_GCLK_ID);
#endif
/* Set the GCLOCK function to the GPIO pin */
gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
}
//!
//! @brief Entry point of the AK5394A task management
//!
void AK5394A_task(void *pvParameters)
{
portTickType xLastWakeTime;
xLastWakeTime = xTaskGetTickCount();
int i;
while (TRUE)
{
// All the hardwork is done by the pdca and the interrupt handler.
// Just check whether sampling freq is changed, to do rate change etc.
vTaskDelayUntil(&xLastWakeTime, configTSK_AK5394A_PERIOD);
if (freq_changed){
if (current_freq.frequency == 96000){
pdca_disable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
pdca_disable(PDCA_CHANNEL_SSC_RX);
gpio_set_gpio_pin(AK5394_DFS0); // L H -> 96khz
gpio_clr_gpio_pin(AK5394_DFS1);
pm_gc_disable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
1, // diven - enabled
0); // divided by 2. Therefore GCLK1 = 6.144Mhz
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
if (Is_usb_full_speed_mode()) FB_rate = 96 << 14;
else FB_rate = (96) << 13;
}
else if (current_freq.frequency == 192000)
{
pdca_disable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
pdca_disable(PDCA_CHANNEL_SSC_RX);
gpio_clr_gpio_pin(AK5394_DFS0); // H L -> 192khz
gpio_set_gpio_pin(AK5394_DFS1);
pm_gc_disable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
0, // diven - disabled
0); // GCLK1 = 12.288Mhz
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
if (Is_usb_full_speed_mode()) FB_rate = 192 << 14;
else FB_rate = (192) << 13;
}
else if (current_freq.frequency == 48000) // 48khz
{
pdca_disable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
pdca_disable(PDCA_CHANNEL_SSC_RX);
gpio_clr_gpio_pin(AK5394_DFS0); // L L -> 48khz
gpio_clr_gpio_pin(AK5394_DFS1);
pm_gc_disable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
1, // diven - enabled
1); // divided by 4. Therefore GCLK1 = 3.072Mhz
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
if (Is_usb_full_speed_mode()) FB_rate = 48 << 14;
else FB_rate = (48) << 13;
}
// re-sync SSC to LRCK
// Wait for the next frame synchronization event
// to avoid channel inversion. Start with left channel - FS goes low
// However, the channels are reversed at 192khz
if (current_freq.frequency == 192000) {
while (gpio_get_pin_value(AK5394_LRCK));
while (!gpio_get_pin_value(AK5394_LRCK)); // exit when FS goes high
}
else {
while (!gpio_get_pin_value(AK5394_LRCK));
while (gpio_get_pin_value(AK5394_LRCK)); // exit when FS goes low
}
// Enable now the transfer.
pdca_enable(PDCA_CHANNEL_SSC_RX);
// Init PDCA channel with the pdca_options.
pdca_init_channel(PDCA_CHANNEL_SSC_RX, &PDCA_OPTIONS); // init PDCA channel with options.
pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
// reset freq_changed flag
freq_changed = FALSE;
}
if (usb_alternate_setting_out_changed){
if (usb_alternate_setting_out != 1){
for (i = 0; i < SPK_BUFFER_SIZE; i++){
spk_buffer_0[i] = 0;
spk_buffer_1[i] = 0;
}
};
usb_alternate_setting_out_changed = FALSE;
}
}
}
//!
//! @brief This function initializes the hardware/software resources
//! required for device CDC task.
//!
void AK5394A_task_init(void)
{
// Set up CS4344
// Set up GLCK1 to provide master clock for CS4344
gpio_enable_module_pin(GCLK1, GCLK1_FUNCTION); // for DA_SCLK
// LRCK is SCLK / 64 generated by TX_SSC
// so SCLK of 6.144Mhz ===> 96khz
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_GCLK1, // gc
0, // osc_or_pll: use Osc (if 0) or PLL (if 1)
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1
1, // diven - enabled
0); // divided by 2. Therefore GCLK1 = 6.144Mhz
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_GCLK1);
pm_enable_osc1_ext_clock(&AVR32_PM); // OSC1 is clocked by 12.288Mhz Osc
// from AK5394A Xtal Oscillator
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set up AK5394A
gpio_clr_gpio_pin(AK5394_RSTN); // put AK5394A in reset
gpio_clr_gpio_pin(AK5394_DFS0); // L L -> 48khz
gpio_clr_gpio_pin(AK5394_DFS1);
gpio_set_gpio_pin(AK5394_HPFE); // enable HP filter
gpio_clr_gpio_pin(AK5394_ZCAL); // use VCOML and VCOMR to cal
gpio_set_gpio_pin(AK5394_SMODE1); // SMODE1 = H for Master i2s
gpio_set_gpio_pin(AK5394_SMODE2); // SMODE2 = H for Master/Slave i2s
gpio_set_gpio_pin(AK5394_RSTN); // start AK5394A
while (gpio_get_pin_value(AK5394_CAL)); // wait till CAL goes low
// Assign GPIO to SSC.
gpio_enable_module(SSC_GPIO_MAP, sizeof(SSC_GPIO_MAP) / sizeof(SSC_GPIO_MAP[0]));
gpio_enable_pin_glitch_filter(SSC_RX_CLOCK);
gpio_enable_pin_glitch_filter(SSC_RX_DATA);
gpio_enable_pin_glitch_filter(SSC_RX_FRAME_SYNC);
gpio_enable_pin_glitch_filter(SSC_TX_CLOCK);
gpio_enable_pin_glitch_filter(SSC_TX_DATA);
gpio_enable_pin_glitch_filter(SSC_TX_FRAME_SYNC);
current_freq.frequency = 96000;
// set up SSC
ssc_i2s_init(ssc, 96000, 24, 32, SSC_I2S_MODE_STEREO_OUT_STEREO_IN, FPBA_HZ);
// set up PDCA
// In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix
// provides specific logic in order to re-arbitrate before the end of the INCR transfer.
//
// HSB Bus Matrix: By default the HSB bus matrix mode is in Undefined length burst type (INCR).
// Here we have to put in single access (the undefined length burst is treated as a succession of single
// accesses, allowing re-arbitration at each beat of the INCR burst.
// Refer to the HSB bus matrix section of the datasheet for more details.
//
// HSB Bus matrix register MCFG1 is associated with the CPU instruction master interface.
AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_CPU_INSN] = 0x1;
audio_buffer_in = 0;
spk_buffer_out = 0;
// Register PDCA IRQ interrupt.
pdca_set_irq();
// Init PDCA channel with the pdca_options.
pdca_init_channel(PDCA_CHANNEL_SSC_RX, &PDCA_OPTIONS); // init PDCA channel with options.
pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_RX);
pdca_init_channel(PDCA_CHANNEL_SSC_TX, &SPK_PDCA_OPTIONS); // init PDCA channel with options.
pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_SSC_TX);
//////////////////////////////////////////////
// Enable now the transfer.
pdca_enable(PDCA_CHANNEL_SSC_TX);
xTaskCreate(AK5394A_task,
configTSK_AK5394A_NAME,
configTSK_AK5394A_STACK_SIZE,
NULL,
configTSK_AK5394A_PRIORITY,
NULL);
}
void board_init(void)
{
// first change to OSC0 (12MHz)
pm_enable_osc0_crystal(& AVR32_PM, FOSC0); // Enable the Osc0 in crystal mode
pm_enable_clk0(& AVR32_PM, OSC0_STARTUP); // Crystal startup time
pm_switch_to_clock(& AVR32_PM, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
pm_enable_osc1_ext_clock(& AVR32_PM); // ocs1 is external clock
pm_enable_clk1(& AVR32_PM, OSC1_STARTUP);
pm_pll_setup(&AVR32_PM
, 0 // pll
, 3 // mul
, 0 // div -> f_vfo = 16.384 MHz * 8 = 131.072 MHz
, 1 // osc
, 16 // lockcount
);
pm_pll_set_option(&AVR32_PM
, 0 // pll
, 1 // pll_freq (f_vfo range 80MHz - 180 MHz)
, 1 // pll_div2 (f_pll1 = f_vfo / 2)
, 0 // pll_wbwdisable
);
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
pm_cksel(&AVR32_PM
, 1, 1 // PBA (CPU / 4) = 16.384 MHz
, 0, 0 // PBB 65.536 MHz
, 0, 0 // HSB = CPU 65.536 MHz
);
flashc_set_wait_state(1); // one wait state if CPU clock > 33 MHz
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); // switch to PLL0
// --------------------------------------
// USB clock
// Use 12MHz from OSC0 and generate 96 MHz
pm_pll_setup(&AVR32_PM, 1, // pll.
7, // mul.
1, // div.
0, // osc.
16); // lockcount.
pm_pll_set_option(&AVR32_PM, 1, // pll.
1, // pll_freq: choose the range 80-180MHz.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL1 and wait forl lock
pm_pll_enable(&AVR32_PM, 1);
// Wait for PLL1 locked.
pm_wait_for_pll1_locked(&AVR32_PM);
pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc.
1, // osc_or_pll: use Osc (if 0) or PLL (if 1).
1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
0, // diven.
0); // div.
pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
// --------------------------------------
// LCD display
gpio_enable_gpio( lcd_gpio_map, sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] ) );
int i;
for (i=0; i < (sizeof( lcd_gpio_map ) / sizeof( lcd_gpio_map[0] )); i++)
{
gpio_configure_pin( lcd_gpio_map[i].pin, lcd_gpio_map[i].function);
}
gpio_enable_module( lcd_pwm_gpio_map, sizeof( lcd_pwm_gpio_map ) / sizeof( lcd_pwm_gpio_map[0] ) );
// Backlight
AVR32_PWM.channel[6].CMR.cpre = 3;
AVR32_PWM.channel[6].cprd = 1000;
AVR32_PWM.channel[6].cdty = 500;
AVR32_PWM.ENA.chid6 = 1;
// contrast
AVR32_PWM.channel[0].CMR.cpre = 3;
AVR32_PWM.channel[0].cprd = 1000;
AVR32_PWM.channel[0].cdty = 520;
AVR32_PWM.ENA.chid0 = 1;
// switches
gpio_enable_gpio( switch_gpio_map, sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] ) );
for (i=0; i < (sizeof( switch_gpio_map ) / sizeof( switch_gpio_map[0] )); i++)
{
gpio_configure_pin( switch_gpio_map[i].pin, switch_gpio_map[i].function);
}
// USART
gpio_enable_module( usart_gpio_map, sizeof( usart_gpio_map ) / sizeof( usart_gpio_map[0] ) );
}
/**
* @brief Start PLL @ 48Mhz to run with
*/
void Start_PLL(void)
{
volatile avr32_pm_t *pm = &AVR32_PM;
// Switch the main clock to OSC0
pm_switch_to_osc0(pm, BOARD_OSC0_HZ, BOARD_OSC0_STARTUP_US);
// For FOSC0 = 12.288 MHz:
// Setup PLL0 on OSC0, mul=15 ,no divisor, lockcount=16, ie. 12 MHz x 16 = 196.608 MHz output.
// Division by 2 (in options) yields PLL0 output as 98.304 MHz.
// The formula is here:
// if (PLLDIV > 0)
// fVCO = (PLLMUL+1)/(PLLDIV) • fOSC;
// else
// fVCO = 2*(PLLMUL+1) • fOSC;
// Lock count defines the PLL settling time (0x00 .. 0x3F.)
pm_pll_setup(
pm, // volatile avr32_pm_t *pm
0, // PLL number(0 for PLL0, 1 for PLL1)
15, // PLL MUL in the PLL formula
1, // PLL DIV in the PLL formula
0, // OSC number (0 for osc0, 1 for osc1)
16); // unsigned int lockcount
// Set PLL options to run @ 96 MHz
pm_pll_set_option(
pm, // volatile avr32_pm_t *pm
0, // PLL number(0 for PLL0, 1 for PLL1)
0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz
1, // Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
0); // 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode allow a faster startup time and
// out-of-lock time). 0 to enable the Wide-Bandwidth Mode.
// Enable PLL0 and wait for it to lock.
pm_pll_enable(pm, 0);
pm_wait_for_pll0_locked(pm);
#if 0
#if defined(BOARD_OSC1_HZ)
// We need to enable the crystal by hand. We didn't need to do that for OSC0
// because the call to pm_switch_to_osc0() contains all that housekeeping.
// But here we don't want to "switch to" the crystal.
pm_enable_osc1_crystal(pm, BOARD_OSC1_HZ); // Enable the OSC1 in crystal mode
pm_enable_clk1(pm, BOARD_OSC1_STARTUP_US);
// For FOSC1 = 12.000 MHz:
// Setup PLL1 on OSC1, mul=15 ,no divisor, ie. 12 MHz x 15 = 180 MHz output.
// Division by 2 (in options) yields PLL0 output as 96.000 MHz.
// Lock count defines the PLL settling time (0x00 .. 0x3F.)
// The formula is here:
// if (PLLDIV > 0)
// fVCO = (PLLMUL+1)/(PLLDIV) • fOSC;
// else
// fVCO = 2*(PLLMUL+1) • fOSC;
pm_pll_setup(
pm, // volatile avr32_pm_t *pm
1, // PLL number(0 for PLL0, 1 for PLL1)
15, // PLL MUL in the PLL formula
1, // PLL DIV in the PLL formula
1, // OSC number (0 for osc0, 1 for osc1)
16); // unsigned int lockcount
// Set PLL options to run @ 96.000 MHz
pm_pll_set_option(
pm, // volatile avr32_pm_t *pm
1, // PLL number(0 for PLL0, 1 for PLL1)
0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz
1, // Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
0); // 1 Disable the Wide-Bandwidth Mode (Wide-Bandwidth mode allow a faster startup time and
// out-of-lock time). 0 to enable the Wide-Bandwidth Mode.
// Enable PLL1 and wait for it to lock.
pm_pll_enable(pm, 1);
pm_wait_for_pll1_locked(pm);
#endif /* defined(BOARD_OSC1_HZ) */
#endif
// Select clocks as follows, considering that we are fed with PLL0 (98.304 MHz)
// fHSB = fMain/2, or 49.152 MHz
// fPBA = fMain/8, or 12.288 MHz
// fPBB = fMain/2, or 49.152 MHz
// ========================================
// The formula (applies to all three channels, they are the same.)
//
// if (xDIV) // Is the divisor enabled?
// fBUS = fMain / 2^(xSEL+1); // Yes
// else
// fBUS = fMain; // No
pm_cksel(
pm, // volatile avr32_pm_t *pm
true, // PBADIV: Peripheral Bus A clock divisor enable
0, // PBASEL: Peripheral Bus A divisor tap (fPBA = fMain/2, or 49.152 MHz)
true, // PBBDIV: Peripheral Bus B clock divisor enable
0, // PBBSEL: Peripheral Bus B select (fPBB = fMain/2, or 49.152 MHz)
1, // CPUDIV: CPU/HSB clock divisor enable
0); // CPUSEL: CPU/HSB clock divisor tap (fHSB = fMain/2, or 49.152 MHz)
// One wait state at 48 MHz (required at fHSB > 33 MHz)
flashc_set_wait_state(1);
// Select the PLL0 as the clock source.
pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_PLL0);
#if 0
#if defined(BOARD_OSC1_HZ)
// Timers, communication modules, and other modules connected to external circuitry may require
// specific clock frequencies to operate correctly. The Power Manager contains an implementation
// defined number of generic clocks that can provide a wide range of accurate clock frequencies.
// Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
// can optionally be divided by any even integer up to 512. Each clock can be independently
// enabled and disabled, and is also automatically disabled along with peripheral clocks by the
// Sleep Controller.
// Setup generic clock number 0 on PLL, with OSC0/PLL0, no divisor.
// A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
// either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
// The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
// resulting in the output frequency:
//
// fGCLK = fSRC / (2*(DIV+1))
//
// In this particular case we enable the generic clock to the USB module. Since the PLL1 is
// producing 96.000 MHz we want to divide it by 2 to whittle it down to 48.000 +/- 0.25%.
// The 48 MHz is the only clock that the USB module can use.
//
pm_gc_setup(
pm, // volatile avr32_pm_t *pm
AVR32_PM_GCLK_USBB, // Generic clock number
1, // Use Osc (=0) or PLL (=1)
1, // Select Osc0/PLL0 or Osc1/PLL1
1, // DIVEN: Generic clock divisor enable
0); // DIV: Generic clock divisor (divide by 2)
// Enable Generic clock 4 */
pm_gc_enable(pm, AVR32_PM_GCLK_USBB);
#endif
#endif
#if 0 // Enable only for debugging, or if you really need to output the generic clock...
pm_gc_setup(
pm, // volatile avr32_pm_t *pm
AVR32_PM_GCLK_GCLK0, // Generic clock number
1, // Use Osc (=0) or PLL (=1)
0, // Select Osc0/PLL0 or Osc1/PLL1
0, // DIVEN: Generic clock divisor enable
1); // DIV: Generic clock divisor (divide by 0)
// Enable Generic clock 0 */
pm_gc_enable(pm, AVR32_PM_GCLK_GCLK0);
/* Output the clock AVR32_PM_GCLK_GCLK0 to a GPIO (PB19) */
gpio_enable_module_pin(AVR32_PM_GCLK_0_1_PIN, AVR32_PM_GCLK_0_1_FUNCTION);
#endif
}
//!
//! \fn main
//! \brief start the software here
//! 1) Initialize the microcontroller and the shared hardware resources
//! of the board.
//! 2) Launch the IP modules.
//! 3) Start FreeRTOS.
//! \return 42, which should never occur.
//! \note
//!
int main( void )
{
volatile avr32_pm_t* pm = &AVR32_PM;
/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
/* Switch to external oscillator 0 */
pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
Extra div by 2 => 96MHz */
pm_pll_setup(pm, /* volatile avr32_pm_t* pm */
0, /* unsigned int pll */
15, /* unsigned int mul */
1, /* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
0, /* unsigned int osc */
16); /* unsigned int lockcount */
pm_pll_set_option( pm, 0, // pll0
0, // Choose the range 160-240MHz.
1, // div2
0 ); // wbwdisable
/* Enable PLL0 */
pm_pll_enable(pm,0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(pm) ;
/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
pm_gc_setup(pm,
0,
1, /* Use Osc (=0) or PLL (=1) */
0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
0,
1);
/* Enable Generic clock 0*/
pm_gc_enable(pm, 0);
/* switch to clock */
pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
flashc_set_wait_state( 1 );
pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
/* Setup the LED's for output. */
vParTestInitialise();
/* Start the flash tasks just to provide visual feedback that the demo is
executing. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
/* 2) Start ethernet task. */
vStartEthernetTask( mainETH_TASK_PRIORITY );
/* 3) Start FreeRTOS. */
vTaskStartScheduler();
/* Will only reach here if there was insufficient memory to create the idle task. */
return 0;
}