static void mainboard_init(void *chip_info)
{
const struct sci_source *gpes;
size_t num;
int boardid = board_id();
size_t num_gpios;
const struct soc_amd_gpio *gpios;
printk(BIOS_INFO, "Board ID: %d\n", boardid);
mainboard_ec_init();
gpios = variant_gpio_table(&num_gpios);
sb_program_gpios(gpios, num_gpios);
/*
* Some platforms use SCI not generated by a GPIO pin (event above 23).
* For these boards, gpe_configure_sci() is still needed, but all GPIO
* generated events (23-0) must be removed from gpe_table[].
* For boards that only have GPIO generated events, table gpe_table[]
* must be removed, and get_gpe_table() should return NULL.
*/
gpes = get_gpe_table(&num);
if (gpes != NULL)
gpe_configure_sci(gpes, num);
/* Initialize i2c busses that were not initialized in bootblock */
i2c_soc_init();
/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
GPP_CLK2_REQ_MAP_MASK,
GPP_CLK2_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
GPP_CLK0_REQ_MAP_MASK,
GPP_CLK0_REQ_MAP_CLK_REQ0 <<
GPP_CLK0_REQ_MAP_SHIFT);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u32 dword;
u8 byte;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
memcpy(mc->mpc_oem, "AMD ", 8);
smp_write_processors(mc);
//mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
my_smp_write_bus(mc, bus_isa, "ISA ");
/* I/O APICs: APIC ID Version State Address */
dword = 0;
dword = pm_read8(0x34) & 0xF0;
dword |= (pm_read8(0x35) & 0xFF) << 8;
dword |= (pm_read8(0x36) & 0xFF) << 16;
dword |= (pm_read8(0x37) & 0xFF) << 24;
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_hudson = IO_APIC_ID;
smp_write_ioapic(mc, apicid_hudson, 0x21, dword);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_hudson[1], 0x5, 0x0, 0x14);
PCI_INT(bus_hudson[1], 0x5, 0x1, 0x15);
PCI_INT(bus_hudson[1], 0x5, 0x2, 0x16);
PCI_INT(bus_hudson[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_hudson[1], 0x6, 0x0, 0x15);
PCI_INT(bus_hudson[1], 0x6, 0x1, 0x16);
PCI_INT(bus_hudson[1], 0x6, 0x2, 0x17);
PCI_INT(bus_hudson[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_hudson[1], 0x7, 0x0, 0x16);
PCI_INT(bus_hudson[1], 0x7, 0x1, 0x17);
PCI_INT(bus_hudson[1], 0x7, 0x2, 0x14);
PCI_INT(bus_hudson[1], 0x7, 0x3, 0x15);
PCI_INT(bus_hudson[2], 0x0, 0x0, 0x12);
PCI_INT(bus_hudson[2], 0x0, 0x1, 0x13);
PCI_INT(bus_hudson[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);
/* FCH PCIe PortA */
PCI_INT(0x0, 0x15, 0x0, 0x10);
/* FCH PCIe PortB */
PCI_INT(0x0, 0x15, 0x1, 0x11);
/* FCH PCIe PortC */
PCI_INT(0x0, 0x15, 0x2, 0x12);
/* FCH PCIe PortD */
PCI_INT(0x0, 0x15, 0x3, 0x13);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
return mptable_finalize(mc);
}
