_mali_osk_errcode_t mali_pmm_pmu_powerup(u32 cores)
{
u32 cores_pmu;
u32 stat;
u32 timeout;
MALI_DEBUG_ASSERT_POINTER(pmu_info);
MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power up (0x%x)\n", cores) );
/* Don't use interrupts - just poll status */
pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_INT_MASK, 0 );
cores_pmu = pmu_translate_cores_to_pmu(cores);
pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_UP, cores_pmu );
timeout = 10; /* 10ms */
do
{
/* Get status of sleeping cores */
stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
stat &= cores_pmu;
if( stat == 0 ) break; /* All cores we wanted are now awake */
_mali_osk_time_ubusydelay(1000); /* 1ms */
timeout--;
} while( timeout > 0 );
if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
MALI_SUCCESS;
}
void _mali_pmm_pmu_power_down( platform_pmu_t *pmu, u32 cores, mali_bool immediate_only )
{
u32 cores_pmu;
u32 stat;
u32 timeout;
MALI_DEBUG_ASSERT_POINTER( pmu );
MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: test power down (0x%x)\n", cores) );
cores_pmu = pmu_translate_cores_to_pmu(cores);
pmu_reg_write( pmu, (u32)PMU_REG_ADDR_MGMT_POWER_DOWN, cores_pmu );
/* Wait for cores to be powered down */
timeout = 10; /* 10ms */
do
{
/* Get status of sleeping cores */
stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
stat &= cores_pmu;
if( stat == cores_pmu ) break; /* All cores we wanted are now asleep */
_mali_osk_time_ubusydelay(1000); /* 1ms */
timeout--;
} while( timeout > 0 );
return;
}
_mali_osk_errcode_t mali_platform_powerdown(u32 cores)
{
#if USING_MALI_PMM
u32 stat;
u32 timeout;
u32 cores_pmu;
MALI_DEBUG_ASSERT_POINTER(pmu_info);
MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power down (0x%x)\n", cores) );
cores_pmu = pmu_translate_cores_to_pmu(cores);
pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_DOWN, cores_pmu );
/* Wait for cores to be powered down */
timeout = 10; /* 10ms */
do
{
/* Get status of sleeping cores */
stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
stat &= cores_pmu;
if( stat == cores_pmu ) break; /* All cores we wanted are now asleep */
_mali_osk_time_ubusydelay(1000); /* 1ms */
timeout--;
} while( timeout > 0 );
if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
MALI_SUCCESS;
#else
/* Nothing to do when not using PMM */
MALI_SUCCESS;
#endif
}
static void pmu_dump_regs( platform_pmu_t *pmu )
{
u32 addr;
for( addr = 0x0; addr < PMU_REGISTER_ADDRESS_SPACE_SIZE; addr += 0x4 )
{
MALI_PRINT( ("PMU_REG: 0x%08x: 0x%04x\n", (addr + pmu->reg_base_addr), pmu_reg_read( pmu, addr ) ) );
}
}
u32 _mali_pmm_pmu_irq_power_up( platform_pmu_t *pmu )
{
u32 reg_read = 0;
MALI_DEBUG_ASSERT_POINTER( pmu );
reg_read = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_INT_CLEAR );
return reg_read;
}
_mali_osk_errcode_t mali_platform_powerup(u32 cores)
{
#if USING_MALI_PMM
u32 cores_pmu;
u32 stat;
u32 timeout;
MALI_DEBUG_ASSERT_POINTER(pmu_info);
MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */
MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power up (0x%x)\n", cores) );
/*enable mali axi/apb clock*/
if(mali_clk_flag == 0)
{
//printk(KERN_WARNING "enable mali clock\n");
//MALI_PRINT(("enable mali clock\n"));
mali_clk_flag = 1;
if(clk_enable(h_ahb_mali))
{
MALI_PRINT(("try to enable mali ahb failed!\n"));
}
if(clk_enable(h_mali_clk))
{
MALI_PRINT(("try to enable mali clock failed!\n"));
}
}
/* Don't use interrupts - just poll status */
pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_INT_MASK, 0 );
cores_pmu = pmu_translate_cores_to_pmu(cores);
pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_UP, cores_pmu );
timeout = 10; /* 10ms */
do
{
/* Get status of sleeping cores */
stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS );
stat &= cores_pmu;
if( stat == 0 ) break; /* All cores we wanted are now awake */
_mali_osk_time_ubusydelay(1000); /* 1ms */
timeout--;
} while( timeout > 0 );
if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT);
MALI_SUCCESS;
#else
/* Nothing to do when not using PMM */
MALI_SUCCESS;
#endif
}
/* This function is an internal test for the PMU without any Mali h/w interaction */
static void pmu_test( platform_pmu_t *pmu, u32 cores )
{
u32 stat;
u32 timeout;
MALI_PRINT( ("PMU_TEST: Start\n") );
pmu_dump_regs( pmu );
MALI_PRINT( ("PMU_TEST: Power down cores: 0x%x\n", cores) );
_mali_pmm_pmu_power_down( pmu, cores, MALI_TRUE );
stat = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_STATUS );
MALI_PRINT( ("PMU_TEST: %s\n", (stat & cores) == cores ? "SUCCESS" : "FAIL" ) );
pmu_dump_regs( pmu );
MALI_PRINT( ("PMU_TEST: Power up cores: 0x%x\n", cores) );
_mali_pmm_pmu_power_up( pmu, cores, MALI_FALSE );
MALI_PRINT( ("PMU_TEST: Waiting for power up...\n") );
timeout = 1000; /* 1 sec */
while( !_mali_pmm_pmu_irq_power_up(pmu) && timeout > 0 )
{
_mali_osk_time_ubusydelay(1000); /* 1ms */
timeout--;
}
MALI_PRINT( ("PMU_TEST: Waited %dms for interrupt\n", (1000-timeout)) );
stat = pmu_reg_read( pmu, (u32)PMU_REG_ADDR_MGMT_STATUS );
MALI_PRINT( ("PMU_TEST: %s\n", (stat & cores) == 0 ? "SUCCESS" : "FAIL" ) );
_mali_pmm_pmu_irq_power_up_clear(pmu);
pmu_dump_regs( pmu );
MALI_PRINT( ("PMU_TEST: Finish\n") );
}
u32 pmu_get_power_up_down_info(void)
{
return pmu_reg_read(pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS);
}
