void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *muxctl = &pmt->pmt_ctl[pin];
int i, mux = -1;
u32 reg;
/* Error check on pin and func */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_func_isvalid(func));
/* Handle special values */
if (func == PMUX_FUNC_SAFE)
func = tegra_soc_pingroups[pin].func_safe;
if (func & PMUX_FUNC_RSVD) {
mux = func & 0x3;
} else {
/* Search for the appropriate function */
for (i = 0; i < 4; i++) {
if (tegra_soc_pingroups[pin].funcs[i] == func) {
mux = i;
break;
}
}
}
assert(mux != -1);
reg = readl(muxctl);
reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
reg |= (mux << PMUX_MUXCTL_SHIFT);
writel(reg, muxctl);
}
static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_lock = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and lock */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
if (lock == PMUX_PIN_LOCK_DEFAULT)
return 0;
reg = readl(pin_lock);
reg &= ~(0x1 << PMUX_LOCK_SHIFT);
if (lock == PMUX_PIN_LOCK_ENABLE)
reg |= (0x1 << PMUX_LOCK_SHIFT);
else {
/* lock == DISABLE, which isn't possible */
printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
__func__, lock);
}
writel(reg, pin_lock);
return 0;
}
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_io = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and io */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_io_isvalid(io));
reg = readl(pin_io);
reg &= ~(0x1 << PMUX_IO_SHIFT);
reg |= (io & 0x1) << PMUX_IO_SHIFT;
writel(reg, pin_io);
}
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pull = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and pupd */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_pupd_isvalid(pupd));
reg = readl(pull);
reg &= ~(0x3 << PMUX_PULL_SHIFT);
reg |= (pupd << PMUX_PULL_SHIFT);
writel(reg, pull);
}
void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin */
assert(pmux_pingrp_isvalid(pin));
reg = readl(tri);
if (enable)
reg |= PMUX_TRISTATE_MASK;
else
reg &= ~PMUX_TRISTATE_MASK;
writel(reg, tri);
}
static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_od = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and od */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_od_isvalid(od));
if (od == PMUX_PIN_OD_DEFAULT)
return 0;
reg = readl(pin_od);
reg &= ~(0x1 << PMUX_OD_SHIFT);
if (od == PMUX_PIN_OD_ENABLE)
reg |= (0x1 << PMUX_OD_SHIFT);
writel(reg, pin_od);
return 0;
}
static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_lock = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and lock */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_lock_isvalid(lock));
if (lock == PMUX_PIN_LOCK_DEFAULT)
return 0;
reg = readl(pin_lock);
reg &= ~(0x1 << PMUX_LOCK_SHIFT);
if (lock == PMUX_PIN_LOCK_ENABLE)
reg |= (0x1 << PMUX_LOCK_SHIFT);
writel(reg, pin_lock);
return 0;
}
static int pinmux_set_ioreset(enum pmux_pingrp pin,
enum pmux_pin_ioreset ioreset)
{
struct pmux_tri_ctlr *pmt =
(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *pin_ioreset = &pmt->pmt_ctl[pin];
u32 reg;
/* Error check on pin and ioreset */
assert(pmux_pingrp_isvalid(pin));
assert(pmux_pin_ioreset_isvalid(ioreset));
if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
return 0;
reg = readl(pin_ioreset);
reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
reg |= (0x1 << PMUX_IO_RESET_SHIFT);
writel(reg, pin_ioreset);
return 0;
}
