void __init arch_init_irq(void)
{
unsigned int irq;
/* setup standard internal cpu irqs */
mips_cpu_irq_init();
/* Set IRQ information in irq_desc */
for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
pnx833x_hard_disable_pic_irq(irq);
irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
handle_simple_irq);
}
for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
handle_simple_irq);
/* Set PIC priority limiter register to 0 */
PNX833X_PIC_INT_PRIORITY = 0;
/* Setup GPIO IRQ dispatching */
pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
/* Enable PIC IRQs (HWIRQ2) */
if (cpu_has_vint)
set_vi_handler(4, pic_dispatch);
write_c0_status(read_c0_status() | IE_IRQ2);
}
void __init arch_init_irq(void)
{
unsigned int irq;
/* */
mips_cpu_irq_init();
/* */
for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
pnx833x_hard_disable_pic_irq(irq);
irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
handle_simple_irq);
}
for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
handle_simple_irq);
/* */
PNX833X_PIC_INT_PRIORITY = 0;
/* */
pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
/* */
if (cpu_has_vint)
set_vi_handler(4, pic_dispatch);
write_c0_status(read_c0_status() | IE_IRQ2);
}
static void pnx833x_disable_pic_irq(struct irq_data *d)
{
unsigned long flags;
unsigned int pic_irq = d->irq - PNX833X_PIC_IRQ_BASE;
raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
pnx833x_hard_disable_pic_irq(pic_irq);
raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
}
