void setPLL_single(struct nvkm_devinit *init, u32 reg, struct nvkm_pll_vals *pv) { struct nvkm_device *device = init->subdev.device; int chip_version = device->bios->version.chip; uint32_t oldpll = nvkm_rd32(device, reg); int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t saved_powerctrl_1 = 0; int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); if (oldpll == pll) return; /* already set */ if (shift_powerctrl_1 >= 0) { saved_powerctrl_1 = nvkm_rd32(device, 0x001584); nvkm_wr32(device, 0x001584, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1); } if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) /* upclock -- write new post divider first */ nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); else /* downclock -- write new NM first */ nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); if ((chip_version < 0x17 || chip_version == 0x1a) && chip_version != 0x11) /* wait a bit on older chips */ msleep(64); nvkm_rd32(device, reg); /* then write the other half as well */ nvkm_wr32(device, reg, pll); if (shift_powerctrl_1 >= 0) nvkm_wr32(device, 0x001584, saved_powerctrl_1); }
static void setPLL_single(struct nv04_clock_priv *priv, u32 reg, struct nouveau_pll_vals *pv) { int chip_version = nouveau_bios(priv)->version.chip; uint32_t oldpll = nv_rd32(priv, reg); int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t saved_powerctrl_1 = 0; int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); if (oldpll == pll) return; /* already set */ if (shift_powerctrl_1 >= 0) { saved_powerctrl_1 = nv_rd32(priv, 0x001584); nv_wr32(priv, 0x001584, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1); } if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) /* upclock -- write new post divider first */ nv_wr32(priv, reg, pv->log2P << 16 | (oldpll & 0xffff)); else /* downclock -- write new NM first */ nv_wr32(priv, reg, (oldpll & 0xffff0000) | pv->NM1); if (chip_version < 0x17 && chip_version != 0x11) /* wait a bit on older chips */ msleep(64); nv_rd32(priv, reg); /* then write the other half as well */ nv_wr32(priv, reg, pll); if (shift_powerctrl_1 >= 0) nv_wr32(priv, 0x001584, saved_powerctrl_1); }
static void setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv) { struct drm_nouveau_private *dev_priv = dev->dev_private; int chip_version = dev_priv->vbios.chip_version; uint32_t oldpll = NVReadRAMDAC(dev, 0, reg); int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t saved_powerctrl_1 = 0; int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); if (oldpll == pll) return; /* already set */ if (shift_powerctrl_1 >= 0) { saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1); nvWriteMC(dev, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1); } if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) /* upclock -- write new post divider first */ NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff)); else /* downclock -- write new NM first */ NVWriteRAMDAC(dev, 0, reg, (oldpll & 0xffff0000) | pv->NM1); if (chip_version < 0x17 && chip_version != 0x11) /* wait a bit on older chips */ msleep(64); NVReadRAMDAC(dev, 0, reg); /* then write the other half as well */ NVWriteRAMDAC(dev, 0, reg, pll); if (shift_powerctrl_1 >= 0) nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1); }
static void setPLL_double_highregs(struct nv04_clock_priv *priv, u32 reg1, struct nouveau_pll_vals *pv) { int chip_version = nouveau_bios(priv)->version.chip; bool nv3035 = chip_version == 0x30 || chip_version == 0x35; uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); uint32_t oldpll1 = nv_rd32(priv, reg1); uint32_t oldpll2 = !nv3035 ? nv_rd32(priv, reg2) : 0; uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; uint32_t oldramdac580 = 0, ramdac580 = 0; bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ uint32_t saved_powerctrl_1 = 0, savedc040 = 0; int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); /* model specific additions to generic pll1 and pll2 set up above */ if (nv3035) { pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; pll2 = 0; } if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ oldramdac580 = nv_rd32(priv, 0x680580); ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); if (oldramdac580 != ramdac580) oldpll1 = ~0; /* force mismatch */ if (single_stage) /* magic value used by nvidia in single stage mode */ pll2 |= 0x011f; } if (chip_version > 0x70) /* magic bits set by the blob (but not the bios) on g71-73 */ pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; if (oldpll1 == pll1 && oldpll2 == pll2) return; /* already set */ if (shift_powerctrl_1 >= 0) { saved_powerctrl_1 = nv_rd32(priv, 0x001584); nv_wr32(priv, 0x001584, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1); } if (chip_version >= 0x40) { int shift_c040 = 14; switch (reg1) { case 0x680504: shift_c040 += 2; case 0x680500: shift_c040 += 2; case 0x680520: shift_c040 += 2; case 0x680508: shift_c040 += 2; } savedc040 = nv_rd32(priv, 0xc040); if (shift_c040 != 14) nv_wr32(priv, 0xc040, savedc040 & ~(3 << shift_c040)); } if (oldramdac580 != ramdac580) nv_wr32(priv, 0x680580, ramdac580); if (!nv3035) nv_wr32(priv, reg2, pll2); nv_wr32(priv, reg1, pll1); if (shift_powerctrl_1 >= 0) nv_wr32(priv, 0x001584, saved_powerctrl_1); if (chip_version >= 0x40) nv_wr32(priv, 0xc040, savedc040); }
static void setPLL_double_highregs(struct drm_device *dev, uint32_t reg1, struct nouveau_pll_vals *pv) { struct drm_nouveau_private *dev_priv = dev->dev_private; int chip_version = dev_priv->vbios.chip_version; bool nv3035 = chip_version == 0x30 || chip_version == 0x35; uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70); uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1); uint32_t oldpll2 = !nv3035 ? NVReadRAMDAC(dev, 0, reg2) : 0; uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; uint32_t oldramdac580 = 0, ramdac580 = 0; bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ uint32_t saved_powerctrl_1 = 0, savedc040 = 0; int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); /* model specific additions to generic pll1 and pll2 set up above */ if (nv3035) { pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; pll2 = 0; } if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */ oldramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); if (oldramdac580 != ramdac580) oldpll1 = ~0; /* force mismatch */ if (single_stage) /* magic value used by nvidia in single stage mode */ pll2 |= 0x011f; } if (chip_version > 0x70) /* magic bits set by the blob (but not the bios) on g71-73 */ pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; if (oldpll1 == pll1 && oldpll2 == pll2) return; /* already set */ if (shift_powerctrl_1 >= 0) { saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1); nvWriteMC(dev, NV_PBUS_POWERCTRL_1, (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | 1 << shift_powerctrl_1); } if (chip_version >= 0x40) { int shift_c040 = 14; switch (reg1) { case NV_PRAMDAC_MPLL_COEFF: shift_c040 += 2; case NV_PRAMDAC_NVPLL_COEFF: shift_c040 += 2; case NV_RAMDAC_VPLL2: shift_c040 += 2; case NV_PRAMDAC_VPLL_COEFF: shift_c040 += 2; } savedc040 = nvReadMC(dev, 0xc040); if (shift_c040 != 14) nvWriteMC(dev, 0xc040, savedc040 & ~(3 << shift_c040)); } if (oldramdac580 != ramdac580) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_580, ramdac580); if (!nv3035) NVWriteRAMDAC(dev, 0, reg2, pll2); NVWriteRAMDAC(dev, 0, reg1, pll1); if (shift_powerctrl_1 >= 0) nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1); if (chip_version >= 0x40) nvWriteMC(dev, 0xc040, savedc040); }