static int
dfs_set(device_t dev, const struct cf_setting *set)
{
register_t hid1;
if (set == NULL)
return (EINVAL);
hid1 = mfspr(SPR_HID1);
hid1 &= ~(HID1_DFS2 | HID1_DFS4);
if (set->freq == 5000)
hid1 |= HID1_DFS2;
else if (set->freq == 2500)
hid1 |= HID1_DFS4;
/*
* Now set the HID1 register with new values. Calling sequence
* taken from page 2-26 of the MPC7450 family CPU manual.
*/
powerpc_sync();
mtspr(SPR_HID1, hid1);
powerpc_sync(); isync();
return (0);
}
static int
powermac_smp_start_cpu(platform_t plat, struct pcpu *pc)
{
#ifdef SMP
phandle_t cpu;
volatile uint8_t *rstvec;
static volatile uint8_t *rstvec_virtbase = NULL;
int res, reset, timeout;
cpu = pc->pc_hwref;
res = OF_getprop(cpu, "soft-reset", &reset, sizeof(reset));
if (res < 0) {
reset = 0x58;
switch (pc->pc_cpuid) {
case 0:
reset += 0x03;
break;
case 1:
reset += 0x04;
break;
case 2:
reset += 0x0f;
break;
case 3:
reset += 0x10;
break;
default:
return (ENXIO);
}
}
ap_pcpu = pc;
if (rstvec_virtbase == NULL)
rstvec_virtbase = pmap_mapdev(0x80000000, PAGE_SIZE);
rstvec = rstvec_virtbase + reset;
*rstvec = 4;
powerpc_sync();
(void)(*rstvec);
powerpc_sync();
DELAY(1);
*rstvec = 0;
powerpc_sync();
(void)(*rstvec);
powerpc_sync();
timeout = 10000;
while (!pc->pc_awake && timeout--)
DELAY(100);
return ((pc->pc_awake) ? 0 : EBUSY);
#else
/* No SMP support */
return (ENXIO);
#endif
}
static int
ps3_smp_start_cpu(platform_t plat, struct pcpu *pc)
{
/* loader(8) is spinning on 0x40 == 0 right now */
uint32_t *secondary_spin_sem = (uint32_t *)(0x40);
int timeout;
if (pc->pc_hwref != 1)
return (ENXIO);
ap_pcpu = pc;
*secondary_spin_sem = 1;
powerpc_sync();
DELAY(1);
timeout = 10000;
while (!pc->pc_awake && timeout--)
DELAY(100);
return ((pc->pc_awake) ? 0 : EBUSY);
}
static int
chrp_smp_start_cpu(platform_t plat, struct pcpu *pc)
{
cell_t start_cpu;
int result, err, timeout;
if (!rtas_exists()) {
printf("RTAS uninitialized: unable to start AP %d\n",
pc->pc_cpuid);
return (ENXIO);
}
start_cpu = rtas_token_lookup("start-cpu");
if (start_cpu == -1) {
printf("RTAS unknown method: unable to start AP %d\n",
pc->pc_cpuid);
return (ENXIO);
}
ap_pcpu = pc;
powerpc_sync();
result = rtas_call_method(start_cpu, 3, 1, pc->pc_cpuid, EXC_RST, pc,
&err);
if (result < 0 || err != 0) {
printf("RTAS error (%d/%d): unable to start AP %d\n",
result, err, pc->pc_cpuid);
return (ENXIO);
}
timeout = 10000;
while (!pc->pc_awake && timeout--)
DELAY(100);
return ((pc->pc_awake) ? 0 : EBUSY);
}
int
openpic_attach(device_t dev)
{
struct openpic_softc *sc;
u_int cpu, ipi, irq;
u_int32_t x;
sc = device_get_softc(dev);
sc->sc_dev = dev;
sc->sc_rid = 0;
sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
RF_ACTIVE);
if (sc->sc_memr == NULL) {
device_printf(dev, "Could not alloc mem resource!\n");
return (ENXIO);
}
sc->sc_bt = rman_get_bustag(sc->sc_memr);
sc->sc_bh = rman_get_bushandle(sc->sc_memr);
/* Reset the PIC */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_RESET;
openpic_write(sc, OPENPIC_CONFIG, x);
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
powerpc_sync();
DELAY(100);
}
/* Check if this is a cascaded PIC */
sc->sc_irq = 0;
sc->sc_intr = NULL;
do {
struct resource_list *rl;
rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
if (rl == NULL)
break;
if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
break;
sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->sc_irq, RF_ACTIVE);
/* XXX Cascaded PICs pass NULL trapframes! */
bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
openpic_intr, NULL, dev, &sc->sc_icookie);
} while (0);
/* Reset the PIC */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_RESET;
openpic_write(sc, OPENPIC_CONFIG, x);
while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
powerpc_sync();
DELAY(100);
}
x = openpic_read(sc, OPENPIC_FEATURE);
switch (x & OPENPIC_FEATURE_VERSION_MASK) {
case 1:
sc->sc_version = "1.0";
break;
case 2:
sc->sc_version = "1.2";
break;
case 3:
sc->sc_version = "1.3";
break;
default:
sc->sc_version = "unknown";
break;
}
sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
/*
* PSIM seems to report 1 too many IRQs and CPUs
*/
if (sc->sc_psim) {
sc->sc_nirq--;
sc->sc_ncpu--;
}
if (bootverbose)
device_printf(dev,
"Version %s, supports %d CPUs and %d irqs\n",
sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
/* Reset and disable all interrupts. */
for (irq = 0; irq < sc->sc_nirq; irq++) {
x = irq; /* irq == vector. */
x |= OPENPIC_IMASK;
x |= OPENPIC_POLARITY_NEGATIVE;
x |= OPENPIC_SENSE_LEVEL;
x |= 8 << OPENPIC_PRIORITY_SHIFT;
openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
}
/* Reset and disable all IPIs. */
for (ipi = 0; ipi < 4; ipi++) {
x = sc->sc_nirq + ipi;
x |= OPENPIC_IMASK;
x |= 15 << OPENPIC_PRIORITY_SHIFT;
openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
}
/* we don't need 8259 passthrough mode */
x = openpic_read(sc, OPENPIC_CONFIG);
x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
openpic_write(sc, OPENPIC_CONFIG, x);
/* send all interrupts to cpu 0 */
for (irq = 0; irq < sc->sc_nirq; irq++)
openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
/* clear all pending interrupts from cpu 0 */
for (irq = 0; irq < sc->sc_nirq; irq++) {
(void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
}
for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
powerpc_register_pic(dev, sc->sc_nirq);
/* If this is not a cascaded PIC, it must be the root PIC */
if (sc->sc_intr == NULL)
root_pic = dev;
return (0);
}