/* * Setup the architecture */ static void __init gp3_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; cpm2_reset(); /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("gp3_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 2; pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */ pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 4; /* fixup phy address */ pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base); }
/* ************************************************************************ * * Setup the architecture * */ static void __init tqm834x_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; /* get the core frequency */ freq = binfo->bi_intfreq; /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc83xx_setup_hose(); #endif mpc83xx_early_serial_map(); /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC83xx_MDIO); mdata->irq[0] = MPC83xx_IRQ_EXT1; mdata->irq[1] = MPC83xx_IRQ_EXT1; mdata->irq[2] = -1; mdata->irq[31] = -1; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_IS_REDUCED; pdata->bus_id = 0; pdata->phy_id = 2; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_IS_REDUCED; pdata->bus_id = 0; pdata->phy_id = 1; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
void __init mpc83xx_early_serial_map(void) { #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250) struct uart_port serial_req; #endif struct plat_serial8250_port *pdata; bd_t *binfo = (bd_t *) __res; pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); /* Setup serial port access */ pdata[0].uartclk = binfo->bi_busfreq; pdata[0].mapbase += binfo->bi_immr_base; pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250) memset(&serial_req, 0, sizeof (serial_req)); serial_req.iotype = SERIAL_IO_MEM; serial_req.mapbase = pdata[0].mapbase; serial_req.membase = pdata[0].membase; serial_req.regshift = 0; serial_req.uartclk = pdata[0].uartclk; serial_req.irq = pdata[0].irq; serial_req.line = pdata[0].line; serial_req.flags = pdata[0].flags; if (early_serial_setup(&serial_req) != 0) printk("Early serial init of port 0 failed\n"); #if defined(CONFIG_SERIAL_TEXT_DEBUG) gen550_init(0, &serial_req); #endif #ifdef CONFIG_KGDB_8250 kgdb8250_add_port(0, &serial_req); #endif #endif pdata[1].uartclk = binfo->bi_busfreq; pdata[1].mapbase += binfo->bi_immr_base; pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250) /* Assume gen550_init() doesn't modify serial_req */ serial_req.mapbase = pdata[1].mapbase; serial_req.membase = pdata[1].membase; serial_req.line = pdata[1].line; if (early_serial_setup(&serial_req) != 0) printk("Early serial init of port 1 failed\n"); #if defined(CONFIG_SERIAL_TEXT_DEBUG) gen550_init(1, &serial_req); #endif #ifdef CONFIG_KGDB_8250 kgdb8250_add_port(1, &serial_req); #endif #endif }
void __init ml300_early_serial_map(void) { struct plat_serial8250_port *pdata; int i = 0; pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART); while(pdata && pdata->flags) { pdata->membase = ioremap(pdata->mapbase, 0x100); ml300_early_serial_init(i, pdata); pdata++; i++; } #ifdef CONFIG_SERIAL_8250 if (early_serial_setup(&port) != 0) printk("Early serial init of port %d failed\n", i); #endif #ifdef CONFIG_KGDB_8250 kgdb8250_add_port(i, &port) #endif }
void __init mpc83xx_early_serial_map(void) { #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) struct uart_port serial_req; #endif struct plat_serial8250_port *pdata; bd_t *binfo = (bd_t *) __res; pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART); /* Setup serial port access */ pdata[0].uartclk = binfo->bi_busfreq; pdata[0].mapbase += binfo->bi_immr_base; pdata[0].membase = ioremap(pdata[0].mapbase, 0x100); #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) memset(&serial_req, 0, sizeof (serial_req)); serial_req.iotype = SERIAL_IO_MEM; serial_req.mapbase = pdata[0].mapbase; serial_req.membase = pdata[0].membase; serial_req.regshift = 0; gen550_init(0, &serial_req); #endif pdata[1].uartclk = binfo->bi_busfreq; pdata[1].mapbase += binfo->bi_immr_base; pdata[1].membase = ioremap(pdata[1].mapbase, 0x100); #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) /* Assume gen550_init() doesn't modify serial_req */ serial_req.mapbase = pdata[1].mapbase; serial_req.membase = pdata[1].membase; gen550_init(1, &serial_req); #endif }
/* ************************************************************************ * * Setup the architecture * */ static void __init sbc8560_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("sbc8560_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif #ifdef CONFIG_SERIAL_8250 sbc8560_early_serial_map(); #endif #ifdef CONFIG_SERIAL_TEXT_DEBUG /* Invalidate the entry we stole earlier the serial ports * should be properly mapped */ invalidate_tlbcam_entry(num_tlbcam_entries - 1); #endif /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[25] = MPC85xx_IRQ_EXT6; mdata->irq[26] = MPC85xx_IRQ_EXT7; mdata->irq[31] = -1; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 25; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 26; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
/* ************************************************************************ * * Setup the architecture * */ static void __init mpc8540ads_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("mpc8540ads_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif #ifdef CONFIG_SERIAL_8250 mpc85xx_early_serial_map(); #endif #ifdef CONFIG_SERIAL_TEXT_DEBUG /* Invalidate the entry we stole earlier the serial ports * should be properly mapped */ invalidate_tlbcam_entry(NUM_TLBCAMS - 1); #endif /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 0; /* fixup phy address */ pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 1; /* fixup phy address */ pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC); pdata->board_flags = 0; pdata->interruptPHY = MPC85xx_IRQ_EXT5; pdata->phyid = 3; /* fixup phy address */ pdata->phy_reg_addr += binfo->bi_immr_base; memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
static void __init mpc8560ads_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; struct fs_platform_info *fpi; cpm2_reset(); /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("mpc8560ads_setup_arch()", 0); /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[0] = MPC85xx_IRQ_EXT5; mdata->irq[1] = MPC85xx_IRQ_EXT5; mdata->irq[2] = PHY_POLL; mdata->irq[3] = MPC85xx_IRQ_EXT5; mdata->irq[31] = PHY_POLL; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 0; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; pdata->bus_id = 0; pdata->phy_id = 1; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } init_fcc_ioports(); ppc_sys_device_remove(MPC85xx_CPM_FCC1); fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2); if (fpi) { memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->bus_id = "0:02"; fpi->phy_addr = 2; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1]; } fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3); if (fpi) { memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->macaddr[5] += 1; fpi->bus_id = "0:03"; fpi->phy_addr = 3; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2]; } #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }
static void __init sandpoint_setup_arch(void) { /* Probe for Sandpoint model */ sandpoint_probe_type(); if (sandpoint_is_x2) epic_serial_mode = 0; loops_per_jiffy = 100000000 / HZ; #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif /* Lookup PCI host bridges */ sandpoint_find_bridges(); if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0) { bd_t *bp = (bd_t *)__res; struct plat_serial8250_port *pdata; pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0); if (pdata) { pdata[0].uartclk = bp->bi_busfreq; } #ifdef CONFIG_SANDPOINT_ENABLE_UART1 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1); if (pdata) { pdata[0].uartclk = bp->bi_busfreq; } #else ppc_sys_device_remove(MPC10X_UART1); #endif } printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n"); printk(KERN_INFO "Port by MontaVista Software, Inc. ([email protected])\n"); /* DINK32 12.3 and below do not correctly enable any caches. * We will do this now with good known values. Future versions * of DINK32 are supposed to get this correct. */ if (cpu_has_feature(CPU_FTR_SPEC7450)) /* 745x is different. We only want to pass along enable. */ _set_L2CR(L2CR_L2E); else if (cpu_has_feature(CPU_FTR_L2CR)) /* All modules have 1MB of L2. We also assume that an * L2 divisor of 3 will work. */ _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF); #if 0 /* Untested right now. */ if (cpu_has_feature(CPU_FTR_L3CR)) { /* Magic value. */ _set_L3CR(0x8f032000); } #endif }
static void __init mpc8560ads_setup_arch(void) { bd_t *binfo = (bd_t *) __res; unsigned int freq; struct gianfar_platform_data *pdata; struct gianfar_mdio_data *mdata; struct fs_platform_info *fpi; struct fs_mii_bb_platform_info *bb_pdata; cpm2_reset(); /* get the core frequency */ freq = binfo->bi_intfreq; if (ppc_md.progress) ppc_md.progress("mpc8560ads_setup_arch()", 0); #if !defined(CONFIG_BDI_SWITCH) /* * The Abatron BDI JTAG debugger does not tolerate others * mucking with the debug registers. */ mtspr(SPRN_DBCR0, (DBCR0_IDM)); mtspr(SPRN_DBSR, 0xffffffff); #endif /* Set loops_per_jiffy to a half-way reasonable value, for use until calibrate_delay gets called. */ loops_per_jiffy = freq / HZ; #ifdef CONFIG_PCI /* setup PCI host bridges */ mpc85xx_setup_hose(); #endif /* setup the board related info for the MDIO bus */ mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); mdata->irq[0] = MPC85xx_IRQ_EXT5; mdata->irq[1] = MPC85xx_IRQ_EXT5; mdata->irq[2] = -1; mdata->irq[3] = -1; mdata->irq[31] = -1; bb_pdata = (struct fs_mii_bb_platform_info *) ppc_sys_get_pdata (MPC85xx_MDIO_BB); bb_pdata->irq[0] = -1; bb_pdata->irq[1] = -1; bb_pdata->irq[2] = MPC85xx_IRQ_EXT7; bb_pdata->irq[3] = MPC85xx_IRQ_EXT7; bb_pdata->irq[4] = -1; bb_pdata->irq[31] = -1; /* setup the board related information for the enet controllers */ pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR | FSL_GIANFAR_BRD_PHY_ANEG; pdata->bus_id = 0; pdata->phy_id = 0; memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); } pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); if (pdata) { pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR | FSL_GIANFAR_BRD_PHY_ANEG; pdata->bus_id = 0; pdata->phy_id = 1; memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); } init_fcc_ioports(); ppc_sys_device_remove(MPC85xx_CPM_FCC1); ppc_sys_device_remove(MPC85xx_CPM_SCC1); ppc_sys_device_remove(MPC85xx_CPM_SCC2); ppc_sys_device_remove(MPC85xx_CPM_SCC3); ppc_sys_device_remove(MPC85xx_CPM_SCC4); fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC2); if (fpi) { fpi->board_flags = FS_ENET_BRD_PHY_ANEG; memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->bus_id = "0:02"; fpi->phy_addr = 2; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[1]; } fpi = (struct fs_platform_info *) ppc_sys_get_pdata(MPC85xx_CPM_FCC3); if (fpi) { fpi->board_flags = FS_ENET_BRD_PHY_ANEG; memcpy(fpi->macaddr, binfo->bi_enet2addr, 6); fpi->macaddr[5] += 1; fpi->bus_id = "0:03"; fpi->phy_addr = 3; fpi->dpram_offset = (u32)cpm2_immr->im_dprambase; fpi->fcc_regs_c = (u32)&cpm2_immr->im_fcc_c[2]; } #ifdef CONFIG_MTD mpc85xx_ads_mtd_setup(); #endif #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start) ROOT_DEV = Root_RAM0; else #endif #ifdef CONFIG_ROOT_NFS ROOT_DEV = Root_NFS; #else ROOT_DEV = Root_HDA1; #endif }