void spl_board_init(void) { int ret; struct rk3399_cru *cru = rockchip_get_cru(); /* * The RK3399 resets only 'almost all logic' (see also in the TRM * "3.9.4 Global software reset"), when issuing a software reset. * This may cause issues during boot-up for some configurations of * the application software stack. * * To work around this, we test whether the last reset reason was * a power-on reset and (if not) issue an overtemp-reset to reset * the entire module. * * While this was previously fixed by modifying the various places * that could generate a software reset (e.g. U-Boot's sysreset * driver, the ATF or Linux), we now have it here to ensure that * we no longer have to track this through the various components. */ if (cru->glb_rst_st != 0) rk3399_force_power_on_reset(); /* * Turning the eMMC and SPI back on (if disabled via the Qseven * BIOS_ENABLE) signal is done through a always-on regulator). */ ret = regulators_enable_boot_on(false); if (ret) debug("%s: Cannot enable boot on regulator\n", __func__); preloader_console_init(); }
void board_init_f(ulong dummy) { struct udevice *pinctrl; struct udevice *dev; int ret; ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } /* Set up our preloader console */ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { pr_err("%s: pinctrl init failed: %d\n", __func__, ret); hang(); } ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); if (ret) { pr_err("%s: failed to set up console UART\n", __func__); hang(); } preloader_console_init(); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } }
void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); #ifdef CONFIG_LS2085A arch_cpu_init(); #endif #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif board_early_init_f(); timer_init(); #ifdef CONFIG_LS2085A env_init(); #endif get_clocks(); preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif dram_init(); /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); }
int ph1_pro5_init(const struct uniphier_board_data *bd) { ph1_pro4_sbc_init(bd); support_card_reset(); support_card_init(); led_puts("L0"); memconf_init(bd); led_puts("L1"); ph1_pro5_early_clk_init(bd); led_puts("L2"); led_puts("L3"); #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif led_puts("L4"); led_puts("L5"); return 0; }
/* * early system init of muxing and clocks. */ void s_init(void) { /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ #ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif /* * WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ writel(0xAAAA, &wdtimer->wdtwspr); while (readl(&wdtimer->wdtwwps) != 0x0) ; writel(0x5555, &wdtimer->wdtwspr); while (readl(&wdtimer->wdtwwps) != 0x0) ; #ifdef CONFIG_SPL_BUILD /* Setup the PLLs and the clocks for the peripherals */ pll_init(); /* Enable RTC32K clock */ rtc32k_enable(); /* UART softreset */ u32 regval; enable_uart0_pin_mux(); regval = readl(&uart_base->uartsyscfg); regval |= UART_RESET; writel(regval, &uart_base->uartsyscfg); while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) ; /* Disable smart idle */ regval = readl(&uart_base->uartsyscfg); regval |= UART_SMART_IDLE_EN; writel(regval, &uart_base->uartsyscfg); gd = &gdata; preloader_console_init(); /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); enable_board_pin_mux(); config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); #endif }
void spl_board_init(void) { /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ save_omap_boot_params(); /* Prepare console output */ preloader_console_init(); #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif #ifdef CONFIG_AM33XX am33xx_spl_board_init(); #endif }
static int x86_tpl_init(void) { int ret; debug("%s starting\n", __func__); ret = spl_init(); if (ret) { debug("%s: spl_init() failed\n", __func__); return ret; } ret = arch_cpu_init(); if (ret) { debug("%s: arch_cpu_init() failed\n", __func__); return ret; } ret = arch_cpu_init_dm(); if (ret) { debug("%s: arch_cpu_init_dm() failed\n", __func__); return ret; } preloader_console_init(); ret = print_cpuinfo(); if (ret) { debug("%s: print_cpuinfo() failed\n", __func__); return ret; } return 0; }
void board_init_f(ulong dummy) { ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void spl_board_init(void) { struct udevice *pinctrl; int ret; ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { debug("%s: Cannot find pinctrl device\n", __func__); goto err; } /* Enable debug UART */ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); if (ret) { debug("%s: Failed to set up console UART\n", __func__); goto err; } preloader_console_init(); return; err: printf("%s: Error %d\n", __func__, ret); /* No way to report error here */ hang(); }
void board_init_f(ulong dummy) { #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); #endif /* setup clock gating */ ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* setup AXI */ gpr_init(); board_early_init_f(); /* setup GP timer */ timer_init(); setup_spi(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Linux expects the internal registers to be at 0xf1000000 */ arch_cpu_init(); /* * Pin muxing needs to be done before UART output, since * on A38x the UART pins need some re-muxing for output * to work. */ board_early_init_f(); preloader_console_init(); timer_init(); /* First init the serdes PHY's */ serdes_phy_config(); /* Setup DDR */ ddr3_init(); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; /* * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot * initializes DMA very early (before all board code), so the only * opportunity we have to initialize APBHDMA clocks is in SPL. */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); enable_usdhc_clk(1, 2); arch_cpu_init(); timer_init(); cm_fx6_setup_ecspi(); cm_fx6_setup_uart(); get_clocks(); preloader_console_init(); gpio_direction_output(CM_FX6_GREEN_LED, 1); if (cm_fx6_spl_dram_init()) { puts("!!!ERROR!!! DRAM detection failed!!!\n"); hang(); } memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { switch_to_main_crystal_osc(); /* disable watchdog */ at91_disable_wdt(); /* PMC configuration */ at91_pmc_init(); at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); matrix_init(); redirect_int_from_saic_to_aic(); timer_init(); board_early_init_f(); preloader_console_init(); mem_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { ccgr_init(); arch_cpu_init(); gpr_init(); /* setup GP timer */ timer_init(); displ5_set_iomux_uart_spl(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); displ5_init_ecspi(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); displ5_set_iomux_misc_spl(); /* Initialize and reset WDT in SPL */ hw_watchdog_init(); WATCHDOG_RESET(); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void spl_board_init(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ); /* enable console uart printing */ preloader_console_init(); WATCHDOG_RESET(); arch_early_init_r(); /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ if (is_fpgamgr_user_mode()) { int ret = config_pins(gd->fdt_blob, "shared"); if (ret) return; ret = config_pins(gd->fdt_blob, "fpga"); if (ret) return; } else if (!is_fpgamgr_early_user_mode()) { /* Program IOSSM(early IO release) or full FPGA */ fpgamgr_program(buf, FPGA_BUFSIZ, 0); } /* If the IOSSM/full FPGA is already loaded, start DDR */ if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) ddr_calibration_sequence(); if (!is_fpgamgr_user_mode()) fpgamgr_program(buf, FPGA_BUFSIZ, 0); }
void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); #ifndef CONFIG_TDX_APALIS_IMX6_V1_0 /* Make sure we use dte mode */ setup_dtemode_uart(); #endif /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { lowlevel_clock_init(); #if !defined(CONFIG_WDT_AT91) at91_disable_wdt(); #endif /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ at91_plla_init(CONFIG_SYS_AT91_PLLA); /* PCK = PLLA = 2 * MCK */ at91_mck_init(CONFIG_SYS_MCKR); /* Switch MCK on PLLA output */ at91_mck_init(CONFIG_SYS_MCKR_CSS); #if defined(CONFIG_SYS_AT91_PLLB) /* Configure PLLB */ at91_pllb_init(CONFIG_SYS_AT91_PLLB); #endif /* Enable External Reset */ enable_ext_reset(); /* Initialize matrix */ matrix_init(); gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ timer_init(); /* enable clocks for all PIOs */ #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) at91_periph_clk_enable(ATMEL_ID_PIOAB); at91_periph_clk_enable(ATMEL_ID_PIOCD); #else at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOB); at91_periph_clk_enable(ATMEL_ID_PIOC); #endif #if defined(CONFIG_SPL_SERIAL_SUPPORT) /* init console */ at91_seriald_hw_init(); preloader_console_init(); #endif mem_init(); at91_spl_board_init(); }
void board_init_f(ulong dummy) { int ret; /* * Pin muxing needs to be done before UART output, since * on A38x the UART pins need some re-muxing for output * to work. */ board_early_init_f(); /* Example code showing how to enable the debug UART on MVEBU */ #ifdef EARLY_UART /* * Debug UART can be used from here if required: * * debug_uart_init(); * printch('a'); * printhex8(0x1234); * printascii("string"); */ #endif ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); hang(); } /* Use special translation offset for SPL */ dm_set_translation_offset(0xd0000000 - 0xf1000000); preloader_console_init(); timer_init(); /* Armada 375 does not support SerDes and DDR3 init yet */ #if !defined(CONFIG_ARMADA_375) /* First init the serdes PHY's */ serdes_phy_config(); /* Setup DDR */ ddr3_init(); #endif /* * Return to the BootROM to continue the Marvell xmodem * UART boot protocol. As initiated by the kwboot tool. * * This can only be done by the BootROM and not by the * U-Boot SPL infrastructure, since the beginning of the * image is already read and interpreted by the BootROM. * SPL has no chance to receive this information. So we * need to return to the BootROM to enable this xmodem * UART download. */ if (get_boot_device() == BOOT_DEVICE_UART) return_to_bootrom(); }
/* * This section requires the differentiation between iMX6 Sabre boards, but * for now, it will configure only for the mx6q variant. */ static void spl_dram_init(void) { struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = 2, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ .ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, .refsel = 1, /* Refresh cycles at 32KHz */ .refr = 7, /* 8 refresh commands per refresh cycle */ }; if (is_mx6dqp()) { mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); } else { mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); } } void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* iomux and setup of i2c */ board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { /* Set global data pointer */ gd = &gdata; /* Setup global info */ #ifndef CONFIG_CMD_BURN gd->arch.gi = &ginfo; #else gd->arch.gi = (struct global_info *)CONFIG_SPL_GINFO_BASE; #endif gpio_init(); #ifndef CONFIG_FPGA /* Init uart first */ enable_uart_clk(); #endif #ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); #endif #ifndef CONFIG_FPGA debug("Timer init\n"); timer_init(); #ifdef CONFIG_SPL_REGULATOR_SUPPORT debug("regulator set\n"); spl_regulator_set(); #endif debug("CLK stop\n"); clk_prepare(); debug("PLL init\n"); pll_init(); debug("CLK init\n"); clk_init(); #endif debug("SDRAM init\n"); sdram_init(); debug("SDRAM init ok\n"); #ifdef CONFIG_DDR_TEST ddr_basic_tests(); #endif #ifndef CONFIG_BURNER /* Clear the BSS */ memset(__bss_start, 0, (char *)&__bss_end - __bss_start); debug("board_init_r\n"); board_init_r(NULL, 0); #endif }
void spl_board_init(void) { #ifdef CONFIG_SOC_DM365 dm36x_lowlevel_init(0); #endif #ifdef CONFIG_SOC_DA8XX arch_cpu_init(); #endif preloader_console_init(); }
void board_init_f(ulong dummy) { arch_cpu_init(); gpr_init(); board_early_init_f(); timer_init(); preloader_console_init(); ddr_init(); memset(__bss_start, 0, __bss_end - __bss_start); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { ps7_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); preloader_console_init(); arch_cpu_init(); board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; unsigned int major; #ifdef CONFIG_NAND_BOOT struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; u32 porsr1, pinctl; /* * There is LS1 SoC issue where NOR, FPGA are inaccessible during * NAND boot because IFC signals > IFC_AD7 are not enabled. * This workaround changes RCW source to make all signals enabled. */ porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | DCFG_CCSR_PORSR1_RCW_SRC_I2C); out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), pinctl); #endif /* Clear the BSS */ memset(__bss_start, 0, __bss_end - __bss_start); #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); #endif get_clocks(); #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) fsl_dp_disable_console(); #endif preloader_console_init(); #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); dram_init(); /* Allow OCRAM access permission as R/W */ #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif board_init_r(NULL, 0); }
void board_init_f(ulong dummy) { #if 0 arch_cpu_init(); board_early_init_f(); timer_init(); preloader_console_init(); print_cpuinfo(); board_init_r(NULL, 0); #endif }
/* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM * - no variable global data is available */ void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* setup GP timer */ timer_init(); #ifdef CONFIG_BOARD_POSTCLK_INIT board_postclk_init(); #endif #ifdef CONFIG_FSL_ESDHC get_clocks(); #endif /* Setup IOMUX and configure basics. */ novena_spl_setup_iomux_audio(); novena_spl_setup_iomux_buttons(); novena_spl_setup_iomux_enet(); novena_spl_setup_iomux_fpga(); novena_spl_setup_iomux_i2c(); novena_spl_setup_iomux_pcie(); novena_spl_setup_iomux_sdhc(); novena_spl_setup_iomux_spi(); novena_spl_setup_iomux_uart(); novena_spl_setup_iomux_video(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Start the DDR DRAM */ novena_read_spd(&novena_ddr_info, &novena_ddr3_cfg); mx6dq_dram_iocfg(novena_ddr3_cfg.width, &novena_ddr_ioregs, &novena_grp_ioregs); mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &novena_ddr3_cfg); do_write_level_calibration(); do_dqs_calibration(); printf("Running post-config memory test... "); if (novena_memory_test()) printf("Fail!\n"); else printf("Pass\n"); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
/* * early system init of muxing and clocks. */ void s_init(void) { #ifdef CONFIG_SPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ #ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ wdt_disable(); /* Enable timer */ timer_init(); /* Setup the PLLs and the clocks for the peripherals */ pll_init(); /* Enable RTC32K clock */ rtc32k_enable(); /* Set UART pins */ enable_uart0_pin_mux(); /* Set MMC pins */ enable_mmc1_pin_mux(); /* Set Ethernet pins */ enable_enet_pin_mux(); /* Enable UART */ uart_enable(); gd = &gdata; preloader_console_init(); config_dmm(&evm_lisa_map_regs); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); #endif }
void board_init_f(ulong dummy) { int ret; ret = spl_early_init(); if (ret) { printf("spl_early_init() failed: %d\n", ret); hang(); } preloader_console_init(); /* Disable the ddr secure region setting to make it non-secure */ rk_clrreg(SGRF_DDR_CON0, 0x4000); }
void board_init_f(ulong dummy) { ps7_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* Set global data pointer. */ gd = &gdata; preloader_console_init(); arch_cpu_init(); board_init_r(NULL, 0); }
/* * SPL version of board_init_f() */ void board_init_f(ulong bootflag) { end_align = (u32)__spl_flash_end; /* * On MPC5200, the initial RAM (and gd) is located in the internal * SRAM. So we can actually call the preloader console init code * before calling dram_init(). This makes serial output (printf) * available very early, even before SDRAM init, which has been * an U-Boot priciple from day 1. */ /* * Init global_data pointer. Has to be done before calling * get_clocks(), as it stores some clock values into gd needed * later on in the serial driver. */ /* Pointer is writable since we allocated a register for it */ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); /* * get_clocks() needs to be called so that the serial driver * works correctly */ get_clocks(); /* * Do rudimental console / serial setup */ preloader_console_init(); /* * First we need to initialize the SDRAM, so that the real * U-Boot or the OS (Linux) can be loaded */ dram_init(); /* Clear bss */ memset(__bss_start, '\0', __bss_end - __bss_start); /* * Call board_init_r() (SPL framework version) to load and boot * real U-Boot or OS */ board_init_r(NULL, 0); /* Does not return!!! */ }