// get input given DSP value (use sparingly)
io_t scaler_svf_fc_in(void* scaler, s32 x) {
// value table is monotonic, can binary search
s32 jl = 0;
s32 ju = tabSize - 1;
s32 jm;
print_dbg("\r\n scaler_svf_fc_in, x: 0x");
print_dbg_hex(x);
// binary tree search
while(ju - jl > 1) {
jm = (ju + jl) >> 1;
// value table is always ascending
if(x >= tabVal[jm]) {
jl = jm;
} else {
ju = jm;
}
}
return (u16)jm << inRshift;
}
// switch to master mode and send something, return to slave mode when done.
extern void i2c_tx(u8 chip, u32 addr, u8 addr_len, u32 data_len, void* data) {
while( twi_is_busy() ) {;;}
status = init_master();
print_dbg("\r\nI2C init (master) : ");
if(status==TWI_SUCCESS) { print_dbg("SUCCESS"); } else { print_dbg("FAIL: "); print_dbg_hex(status); }
print_dbg("\r\n chip addr: ");
print_dbg_hex(chip);
print_dbg(", mem addr: ");
print_dbg_hex(addr);
print_dbg(", addr len: ");
print_dbg_hex(addr_len);
print_dbg(", data len: ");
print_dbg_hex(data_len);
print_dbg(", data (1st 4 bytes): ");
print_dbg_hex(*((u32*)(data)));
status = send_master(chip, addr, addr_len, data_len, data);
print_dbg("\r\nI2C tx (master) : ");
if(status==TWI_SUCCESS) { print_dbg("SUCCESS"); } else { print_dbg("FAIL: "); print_dbg_hex(status); }
while( twi_is_busy() ) {;;}
status = init_slave();
print_dbg("\r\nI2C init (slave) : ");
if(status==TWI_SUCCESS) { print_dbg("SUCCESS"); } else { print_dbg("FAIL: "); print_dbg_hex(status);}
}
// read default blackfin
void flash_read_ldr(void) {
#if 1
#else
bfinLdrSize = flash_nvram_data.ldrSize;
print_dbg("\r\n read ldrSize from flash: ");
print_dbg_ulong(bfinLdrSize);
memcpy((void*)bfinLdrData, (void*)flash_nvram_data.ldrData, bfinLdrSize);
// TEST: print module data in RAM
#if 0
for(u32 i = 0; i<bfinLdrSize; i += 4) {
if((i % 16) == 0) {
print_dbg("\r\n");
}
print_dbg(" 0x");
print_dbg_hex(*((u32*)(bfinLdrData + i)));
}
#endif
// print_flash((u32)flash_nvram_data.ldrData, bfinLdrSize);
#endif
}
// set focus
extern void net_monome_set_focus(op_monome_t* op_monome, u8 focus) {
print_dbg("\r\n setting monome device focu, op pointer: 0x");
print_dbg_hex((u32)op_monome);
print_dbg(" , value: ");
print_dbg_ulong(focus);
if(focus > 0) {
if(monomeOpFocus != NULL ){
/// stealing focus, inform the previous holder
monomeOpFocus->focus = 0;
}
monome_grid_key_handler = op_monome->handler;
monomeOpFocus = op_monome;
op_monome->focus = 1;
} else {
// release focus if we had it, otherwise do nothing
if( monomeOpFocus == op_monome) {
monome_grid_key_handler = (monome_handler_t)&dummyHandler;
monomeOpFocus = NULL;
op_monome->focus = 0;
}
}
}
// load bfin executable from the RAM buffer
void bfin_load_buf(void) {
u64 i; /// byte index in .ldr
/////
//// TEST: print contents of buffer
/* print_dbg("\r\n\r\n .ldr buffer for: "); */
/* contents(i=0; i<bfinLdrSize; i++) { */
/* print_dbg("\r\n 0x"); */
/* print_dbg_hex(bfinLdrData[i]); */
/* } */
/* print_dbg("\r\n\r\n"); */
////
/////////
////////////
//// tESTING don't check
#if 0
if(bfinLdrSize > BFIN_LDR_MAX_BYTES) {
print_dbg("\r\n bfin load error: size : "); print_dbg_hex(bfinLdrSize);
return;
}
#endif
///////////////
////////////////
app_pause();
bfin_start_transfer();
for(i=0; i<bfinLdrSize; i++) {
bfin_transfer_byte(bfinLdrData[i]);
}
bfin_end_transfer();
app_resume();
}
//----- external (UHC) functions
uhc_enum_status_t uhi_hid_install(uhc_device_t* dev) {
bool b_iface_supported;
uint16_t conf_desc_lgt;
usb_iface_desc_t *ptr_iface;
if (uhi_hid_dev.dev != NULL) {
return UHC_ENUM_SOFTWARE_LIMIT; // Device already allocated
}
conf_desc_lgt = le16_to_cpu(dev->conf_desc->wTotalLength);
ptr_iface = (usb_iface_desc_t*)dev->conf_desc;
b_iface_supported = false;
// return UHC_ENUM_UNSUPPORTED; // No interface supported
while(conf_desc_lgt) {
switch (ptr_iface->bDescriptorType) {
case USB_DT_INTERFACE:
#if 0
print_dbg("\r\n\r\n");
print_dbg("\r\n iface_desc -> bLength : ");
print_dbg_hex(ptr_iface->bLength);
print_dbg("\r\n iface_desc -> bDescriptorType : ");
print_dbg_hex(ptr_iface->bDescriptorType);
print_dbg("\r\n iface_desc -> bInterfaceNumber : ");
print_dbg_hex(ptr_iface->bInterfaceNumber);
print_dbg("\r\n iface_desc -> bAlternateSetting : ");
print_dbg_hex(ptr_iface->bAlternateSetting);
print_dbg("\r\n iface_desc -> bNumEndpoints : ");
print_dbg_hex(ptr_iface->bNumEndpoints);
print_dbg("\r\n iface_desc -> bInterfaceClass : ");
print_dbg_hex(ptr_iface->bInterfaceClass);
print_dbg("\r\n iface_desc -> bInterfaceSubClass : ");
print_dbg_hex(ptr_iface->bInterfaceSubClass);
print_dbg("\r\n iface_desc -> bInterfaceProtocol : ");
print_dbg_hex(ptr_iface->bInterfaceProtocol);
print_dbg("\r\n iface_desc -> iInterface : ");
print_dbg_hex(ptr_iface->iInterface);
print_dbg("\r\n\r\n");
#endif
/* if ((ptr_iface->bInterfaceClass == HID_CLASS) */
/* && (ptr_iface->bInterfaceProtocol == HID_PROTOCOL_GENERIC) ) { */
/// try looking at all HID classes... mostly to test if our system is sane
if ((ptr_iface->bInterfaceClass == HID_CLASS)) {
// Start allocation endpoint(s)
// print_dbg("\r\n HID device: detected interface");
b_iface_supported = true;
} else {
// Stop allocation endpoint(s)
b_iface_supported = false;
}
break;
case USB_DT_ENDPOINT:
// Allocation of the endpoint
if (!b_iface_supported) {
break;
}
if (!uhd_ep_alloc(dev->address, (usb_ep_desc_t*)ptr_iface)) {
return UHC_ENUM_HARDWARE_LIMIT; // Endpoint allocation fail
}
// print_dbg("\r\n HID device: allocated endpoint");
Assert(((usb_ep_desc_t*)ptr_iface)->bEndpointAddress & USB_EP_DIR_IN);
uhi_hid_dev.ep_in = ((usb_ep_desc_t*)ptr_iface)->bEndpointAddress;
uhi_hid_dev.report_size =
le16_to_cpu(((usb_ep_desc_t*)ptr_iface)->wMaxPacketSize);
uhi_hid_dev.report = malloc(uhi_hid_dev.report_size);
if (uhi_hid_dev.report == NULL) {
Assert(false);
return UHC_ENUM_MEMORY_LIMIT; // Internal RAM allocation fail
}
uhi_hid_dev.dev = dev;
// All endpoints of all interfaces supported allocated
return UHC_ENUM_SUCCESS;
default:
// Ignore descriptor
break;
}
Assert(conf_desc_lgt>=ptr_iface->bLength);
conf_desc_lgt -= ptr_iface->bLength;
ptr_iface = (usb_iface_desc_t*)((uint8_t*)ptr_iface + ptr_iface->bLength);
}
return UHC_ENUM_UNSUPPORTED; // No interface supported
}
// search for specified scaler file and load it to specified buffer
// return 1 on success, 0 on failure
u8 files_load_scaler_name(const char* name, s32* dst, u32 dstSize) {
void* fp;
u32 size = 0;
u32 i;
union { u32 u; s32 s; u8 b[4]; } swap;
u8 ret = 0;
//// test
//s32* p = dst;
///
app_pause();
fp = list_open_file_name(&scalerList, name, "r", &size);
if( fp != NULL) {
print_dbg("\r\n scaler file pointer: 0x");
print_dbg_hex((u32)fp);
#ifdef SCALER_LE
swap.b[3] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[0] = fl_fgetc(fp);
#else
swap.b[0] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[3] = fl_fgetc(fp);
#endif
size = swap.u;
print_dbg("\r\n read size (words): 0x");
print_dbg_ulong(size);
if(size > dstSize) {
print_dbg("\r\n warning: requested scaler data is > target, truncating");
for(i=0; i<dstSize; ++i) {
#ifdef SCALER_LE
swap.b[3] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[0] = fl_fgetc(fp);
#else
swap.b[0] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[3] = fl_fgetc(fp);
#endif
*dst++ = swap.s;
}
} else if (size < dstSize) {
print_dbg("\r\n warning: requested scaler data is < target, padding");
for(i=0; i<size; ++i) {
#ifdef SCALER_LE
swap.b[3] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[0] = fl_fgetc(fp);
#else
swap.b[0] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[3] = fl_fgetc(fp);
#endif
*dst++ = swap.s;
}
// remainder
size = dstSize - size;
for(i=0; i<size; ++i) {
*dst++ = 0;
}
} else {
for(i=0; i<size; ++i) {
#ifdef SCALER_LE
swap.b[3] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[0] = fl_fgetc(fp);
#else
swap.b[0] = fl_fgetc(fp);
swap.b[1] = fl_fgetc(fp);
swap.b[2] = fl_fgetc(fp);
swap.b[3] = fl_fgetc(fp);
#endif
*dst++ = swap.s;
}
}
fl_fclose(fp);
ret = 1;
} else {
print_dbg("\r\n error: fp was null in files_load_scaler_name \r\n");
ret = 0;
}
print_dbg("\r\n finished loading scaler file (?)");
///// TEST: verify
/* for(i=0; i<size; i++) { */
/* print_dbg(" 0x"); print_dbg_hex(p[i]); if((i%4)==0) { print_dbg("\r\n"); } */
/* } */
app_resume();
return ret;
}
/** \brief Main function - init and loop to display ADC values */
int main(void)
{
/* GPIO pin/ADC-function map. */
const gpio_map_t ADCIFB_GPIO_MAP = {
{EXAMPLE_ADCIFB_PIN, EXAMPLE_ADCIFB_FUNCTION}
};
/* ADCIFB Configuration */
adcifb_opt_t adcifb_opt = {
/* Resolution mode */
.resolution = AVR32_ADCIFB_ACR_RES_12BIT,
/* Channels Sample & Hold Time in [0,15] */
.shtim = 15,
.ratio_clkadcifb_clkadc =
(sysclk_get_pba_hz() / EXAMPLE_TARGET_CLK_ADC_FREQ_HZ),
/*
* Startup time in [0,127], where
* Tstartup = startup * 8 * Tclk_adc (assuming Tstartup ~ 15us max)
*/
.startup = 3,
/* ADCIFB Sleep Mode disabled */
.sleep_mode_enable = false
};
uint32_t adc_data;
/* Initialize the system clocks */
sysclk_init();
/* Init debug serial line */
init_dbg_rs232(sysclk_get_pba_hz());
/* Assign and enable GPIO pins to the ADC function. */
gpio_enable_module(ADCIFB_GPIO_MAP,
sizeof(ADCIFB_GPIO_MAP) / sizeof(ADCIFB_GPIO_MAP[0]));
/* Enable and configure the ADCIFB module */
if (adcifb_configure(&AVR32_ADCIFB, &adcifb_opt) != PASS) {
/* Config error. */
while (true) {
gpio_tgl_gpio_pin(LED0_GPIO);
delay_ms(100);
}
}
/* Configure the trigger mode */
/* "No trigger, only software trigger can start conversions". */
if (adcifb_configure_trigger(&AVR32_ADCIFB, AVR32_ADCIFB_TRGMOD_NT, 0)
!= PASS) {
/* Config error. */
while (true) {
gpio_tgl_gpio_pin(LED1_GPIO);
delay_ms(100);
}
}
/* Enable the ADCIFB channel the battery is connected to. */
adcifb_channels_enable(&AVR32_ADCIFB, EXAMPLE_ADCIFB_CHANNEL_MASK);
while (true) {
while (adcifb_is_ready(&AVR32_ADCIFB) != true) {
/* Wait until the ADC is ready to perform a conversion. */
}
/* Start an ADCIFB conversion sequence. */
adcifb_start_conversion_sequence(&AVR32_ADCIFB);
while (adcifb_is_drdy(&AVR32_ADCIFB) != true) {
/* Wait until the converted data is available. */
}
/* Get the last converted data. */
adc_data = adcifb_get_last_data(&AVR32_ADCIFB);
/* Display the current voltage of the battery. */
print_dbg("\x1B[2J\x1B[H\r\nADCIFB Example\r\nHEX Value for "
EXAMPLE_ADCIFB_CHANNEL_NAME " : 0x");
print_dbg_hex(adc_data & AVR32_ADCIFB_LCDR_LDATA_MASK);
print_dbg("\r\n");
delay_ms(500);
/*
* Note1: there is a resistor bridge between the battery and the
* ADC pad on the AT32UC3L-EK. The data converted is thus half
* of
* the battery voltage.
*/
/*
* Note2: if the battery is not in place, the conversion is out
* of
* spec because the ADC input is then higher than ADVREF.
*/
}
}
//int main(void) {
////main function
int main (void) {
u32 waitForCard = 0;
// set up avr32 hardware and peripherals
init_avr32();
print_dbg("\r\n SRAM size: 0x");
print_dbg_hex(smc_get_cs_size(1));
cpu_irq_disable();
/// test the SRAM
sram_test();
cpu_irq_enable();
//memory manager
init_mem();
print_dbg("\r\n init_mem");
// wait for sdcard
print_dbg("\r\n SD check... ");
while (!sd_mmc_spi_mem_check()) {
waitForCard++;
}
print_dbg("\r\nfound SD card. ");
// intialize the FAT filesystem
print_dbg("\r\n init fat");
fat_init();
// setup control logic
print_dbg("\r\n init ctl");
init_ctl();
/* // initialize the application */
/* app_init(); */
/* print_dbg("\r\n init app"); */
// initialize flash:
firstrun = init_flash();
print_dbg("r\n init flash, firstrun: ");
print_dbg_ulong(firstrun);
screen_startup();
// find and load dsp from sdcard
files_search_dsp();
print_dbg("\r\n starting event loop.\r\n");
// dont do startup
startup = 0;
while(1) {
check_events();
}
}
// activate an input node with a value
void net_activate(s16 inIdx, const io_t val, void* op) {
static inode_t* pIn;
s16 pIndex;
u8 vis;
print_dbg("\r\n net_activate, input idx: ");
print_dbg_hex(inIdx);
print_dbg(" , value: ");
print_dbg_hex(val);
print_dbg(" , op index: ");
print_dbg_ulong(net->ins[inIdx].opIdx);
print_dbg(" , input idx: ");
print_dbg_ulong(net->ins[inIdx].opInIdx);
if(!netActive) {
if(op != NULL) {
// if the net isn't active, dont respond to requests from operators
print_dbg(" ... ignoring node activation from op.");
return;
}
}
if(inIdx < 0) {
return;
}
vis = net_get_in_play(inIdx);
print_dbg(" , play visibility flag : ");
print_dbg_ulong(vis);
if(inIdx < net->numIns) {
// this is an op input
pIn = &(net->ins[inIdx]);
print_dbg(" ; input node pointer: 0x"); print_dbg_hex((u32)pIn);
op_set_in_val(net->ops[pIn->opIdx],
pIn->opInIdx,
val);
} else {
// this is a parameter
//// FIXME this is horrible
pIndex = inIdx - net->numIns;
if (pIndex >= net->numParams) { return; }
print_dbg(" ; param index: 0x"); print_dbg_ulong(pIndex);
set_param_value(pIndex, val);
}
/// only process for play mode if we're in play mode
if(pageIdx == ePagePlay) {
print_dbg(" , play mode ");
if(opPlay) {
// operators have focus, do nothing
print_dbg(" , op focus mode");
} else {
// process if play-mode-visibility is set on this input
if(vis) {
print_dbg(" , input enabled");
play_input(inIdx);
}
}
}
}
/**
* \brief Device enumeration step 14
* Enable USB configuration, if unless one USB interface is supported by UHIs.
*
* \param add USB address of the setup request
* \param status Transfer status
* \param payload_trans Number of data transfered during DATA phase
*/
static void uhc_enumeration_step14(
usb_add_t add,
uhd_trans_status_t status,
uint16_t payload_trans)
{
usb_setup_req_t req;
bool b_conf_supported = false;
UNUSED(add);
/////////////////////////////////
///// TESTING
#if UHC_PRINT_DBG
print_dbg("\r\n received device descriptor. ");
print_dbg("\r\n address: ");
print_dbg_hex(uhc_dev_enum -> address);
print_dbg("\r\n speed: ");
print_dbg_hex(uhc_dev_enum -> speed);
print_dbg("\r\n\r\n");
print_dbg("\r\n dev desc -> bLength : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bLength);
print_dbg("\r\n dev desc -> bDescriptorType : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bDescriptorType);
print_dbg("\r\n dev desc -> bcdUSB : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bcdUSB);
print_dbg("\r\n dev desc -> bDeviceClass : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bDeviceClass);
print_dbg("\r\n dev desc -> bDeviceSubClass : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bDeviceSubClass);
print_dbg("\r\n dev desc -> bDeviceProtocol : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bDeviceProtocol);
print_dbg("\r\n dev desc -> bMaxPacketSize0 : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bMaxPacketSize0);
print_dbg("\r\n dev desc -> idVendor : ");
print_dbg_hex(uhc_dev_enum->dev_desc.idVendor);
print_dbg("\r\n dev desc -> idProduct : ");
print_dbg_hex(uhc_dev_enum->dev_desc.idProduct);
print_dbg("\r\n dev desc -> bcdDevice : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bcdDevice);
print_dbg("\r\n dev desc -> iManufacturer : ");
print_dbg_hex(uhc_dev_enum->dev_desc.iManufacturer);
print_dbg("\r\n dev desc -> iProduct : ");
print_dbg_hex(uhc_dev_enum->dev_desc.iProduct);
print_dbg("\r\n dev desc -> iSerialNumber : ");
print_dbg_hex(uhc_dev_enum->dev_desc.iSerialNumber);
print_dbg("\r\n dev desc -> bNumConfigurations : ");
print_dbg_hex(uhc_dev_enum->dev_desc.bNumConfigurations);
print_dbg("\r\n\r\n");
print_dbg("\r\n conf desc -> bLength : ");
print_dbg_hex(uhc_dev_enum->conf_desc->bLength);
print_dbg("\r\n conf desc -> bDescriptorType : ");
print_dbg_hex(uhc_dev_enum->conf_desc->bDescriptorType);
print_dbg("\r\n conf desc -> wTotalLength : ");
print_dbg_hex(uhc_dev_enum->conf_desc->wTotalLength);
print_dbg("\r\n conf desc -> bNumInterfaces : ");
print_dbg_hex(uhc_dev_enum->conf_desc->bNumInterfaces);
print_dbg("\r\n conf desc -> bConfigurationValue : ");
print_dbg_hex(uhc_dev_enum->conf_desc->bConfigurationValue);
print_dbg("\r\n conf desc -> iConfiguration : ");
print_dbg_hex(uhc_dev_enum->conf_desc->iConfiguration);
print_dbg("\r\n conf desc -> bmAttributes : ");
print_dbg_hex(uhc_dev_enum->conf_desc->bmAttributes);
print_dbg("\r\n conf desc -> bMaxPower : ");
print_dbg_hex(uhc_dev_enum->conf_desc->bMaxPower);
#endif
/////////////////////////////////
/////////////////////////////////
if ((status != UHD_TRANS_NOERROR)
|| (payload_trans < sizeof(usb_conf_desc_t))
|| (uhc_dev_enum->conf_desc->bDescriptorType != USB_DT_CONFIGURATION)
|| (payload_trans != le16_to_cpu(uhc_dev_enum->conf_desc->wTotalLength))) {
uhc_enumeration_error((status==UHD_TRANS_DISCONNECT)?
UHC_ENUM_DISCONNECT:UHC_ENUM_FAIL);
return;
}
// Check if unless one USB interface is supported by UHIs
for (uint8_t i = 0; i < UHC_NB_UHI; i++) {
switch (uhc_uhis[i].install(uhc_dev_enum)) {
case UHC_ENUM_SUCCESS:
b_conf_supported = true;
break;
case UHC_ENUM_UNSUPPORTED:
break;
default:
// USB host hardware limitation
// Free all endpoints
uhd_ep_free(UHC_DEVICE_ENUM_ADD,0xFF);
UHC_ENUM_EVENT(uhc_dev_enum,UHC_ENUM_HARDWARE_LIMIT);
// Abort enumeration, set line in suspend mode
uhc_enumeration_suspend();
return;
}
}
if (!b_conf_supported) {
// No USB interface supported
UHC_ENUM_EVENT(uhc_dev_enum, UHC_ENUM_UNSUPPORTED);
// Abort enumeration, set line in suspend mode
uhc_enumeration_suspend();
return;
}
// Enable device configuration
req.bmRequestType = USB_REQ_RECIP_DEVICE
| USB_REQ_TYPE_STANDARD | USB_REQ_DIR_OUT;
req.bRequest = USB_REQ_SET_CONFIGURATION;
req.wValue = uhc_dev_enum->conf_desc->bConfigurationValue;
req.wIndex = 0;
req.wLength = 0;
// print_dbg("\r\n device enumeration successful; calling uhd_setup_request in uhc.c");
if (!uhd_setup_request(UHC_DEVICE_ENUM_ADD,
&req,
NULL,
0,
NULL, uhc_enumeration_step15)) {
uhc_enumeration_error(UHC_ENUM_MEMORY_LIMIT);
return;
}
}
// attempt to allocate a new operator from the static memory pool, return index
s16 net_add_op(op_id_t opId) {
u16 ins, outs;
int i, j;
int idxOld, idxNew;
op_t* op;
s32 numInsSave = net->numIns;
s32 numOutsSave = net->numOuts;
print_dbg("\r\n adding operator; old input count: ");
print_dbg_ulong(numInsSave);
if (net->numOps >= NET_OPS_MAX) {
return -1;
}
print_dbg(" , op class: ");
print_dbg_ulong(opId);
print_dbg(" , size: ");
print_dbg_ulong(op_registry[opId].size);
if (op_registry[opId].size > NET_OP_POOL_SIZE - net->opPoolOffset) {
print_dbg("\r\n op creation failed; op memory pool is exhausted.");
return -1;
}
print_dbg(" ; allocating... ");
op = (op_t*)((u8*)net->opPool + net->opPoolOffset);
// use the class ID to initialize a new object in scratch
print_dbg(" ; op address: 0x");
print_dbg_hex((u32)op);
print_dbg(" ; initializing... ");
op_init(op, opId);
ins = op->numInputs;
outs = op->numOutputs;
if (ins > (NET_INS_MAX - net->numIns)) {
print_dbg("\r\n op creation failed; too many inputs in network.");
return -1;
}
if (outs > (NET_OUTS_MAX - net->numOuts)) {
print_dbg("\r\n op creation failed; too many outputs in network.");
return -1;
}
// add op pointer to list
net->ops[net->numOps] = op;
// advance offset for next allocation
net->opPoolOffset += op_registry[opId].size;
//---- add inputs and outputs to node list
for(i=0; i<ins; ++i) {
net->ins[net->numIns].opIdx = net->numOps;
net->ins[net->numIns].opInIdx = i;
++(net->numIns);
}
for(i=0; i<outs; i++) {
net->outs[net->numOuts].opIdx = net->numOps;
net->outs[net->numOuts].opOutIdx = i;
net->outs[net->numOuts].target = -1;
++(net->numOuts);
}
if(net->numOps > 0) {
// if we added input nodes, need to adjust connections to DSP params
for(i=0; i < numOutsSave; i++) {
/* print_dbg("\r\n checking output no. "); */
/* print_dbg_ulong(i); */
/* print_dbg(" ; target: "); */
/* print_dbg_ulong(net->outs[i].target); */
if(net->outs[i].target >= numInsSave) {
/* print_dbg("\r\n adjusting target after op creation; old op count: "); */
/* print_dbg_ulong(net->numOps); */
/* print_dbg(" , output index: "); */
/* print_dbg_ulong(i); */
/* print_dbg(" , current target "); */
/* print_dbg_ulong(net->outs[i].target); */
/* print_dbg(" , count of inputs in new op: "); */
/* print_dbg_ulong(ins); */
// preset target, add offset for new inputs
net_connect(i, net->outs[i].target + ins);
}
/// do the same in all presets!
for(j=0; j<NET_PRESETS_MAX; j++) {
if(preset_out_enabled(j, i)) {
s16 tar = presets[j].outs[i].target;
if(tar >= numInsSave) {
tar = tar + ins;
presets[j].outs[i].target = tar;
}
}
} // preset loop
} // outs loop
for(i=0; i<NET_PRESETS_MAX; i++) {
// shift parameter nodes in preset data
for(j=net->numParams - 1; j>=0; j--) {
// this was the old param index
idxOld = j + numInsSave;
// copy to new param index
idxNew = idxOld + ins;
if(idxNew >= PRESET_INODES_COUNT) {
print_dbg("\r\n out of preset input nodes in new op creation! ");
continue;
} else {
presets[i].ins[idxNew].value = presets[i].ins[idxOld].value;
presets[i].ins[idxNew].enabled = presets[i].ins[idxOld].enabled;
// clear the old data. it may correspond to new operator inputs.
presets[i].ins[idxOld].enabled = 0;
presets[i].ins[idxOld].value = 0;
}
}
}
}
++(net->numOps);
return net->numOps - 1;
}
/** \brief Main function to initialize the system and loop to display ADC values
*
*/
int main( void )
{
int16_t adc_values[EXAMPLE_ADCIFA_NUMBER_OF_SEQUENCE];
adcifa_sequencer_opt_t adcifa_sequence_opt ;
adcifa_sequencer_conversion_opt_t
adcifa_sequence_conversion_opt[EXAMPLE_ADCIFA_NUMBER_OF_SEQUENCE];
adcifa_opt_t adc_config_t ;
adcifa_window_monitor_opt_t adcifa_window_monitor_0_opt;
adcifa_window_monitor_opt_t adcifa_window_monitor_1_opt;
/* GPIO pin/adc-function map. */
const gpio_map_t ADCIFA_GPIO_MAP = {
{AVR32_ADCREF0_PIN, AVR32_ADCREF0_FUNCTION},
{AVR32_ADCREFP_PIN, AVR32_ADCREFP_FUNCTION},
{AVR32_ADCREFN_PIN, AVR32_ADCREFN_FUNCTION},
{EXAMPLE_ADC_POTENTIOMETER_PIN, EXAMPLE_ADC_POTENTIOMETER_FUNCTION},
{EXAMPLE_ADC_MIC_PIN, EXAMPLE_ADC_MIC_FUNCTION}
};
/* Init system clocks */
sysclk_init();
/* Init debug serial line */
init_dbg_rs232(sysclk_get_cpu_hz());
/* Assign and enable GPIO pins to the ADC function. */
gpio_enable_module(ADCIFA_GPIO_MAP, sizeof(ADCIFA_GPIO_MAP) /
sizeof(ADCIFA_GPIO_MAP[0]));
/* Configure the ADC for the application*/
adc_config_t.frequency = 1000000;
adc_config_t.reference_source = ADCIFA_ADCREF0;
adc_config_t.sample_and_hold_disable = false;
adc_config_t.single_sequencer_mode = false;
adc_config_t.free_running_mode_enable = false;
adc_config_t.sleep_mode_enable = false;
adc_config_t.mux_settle_more_time = false;
/* Get ADCIFA Factory Configuration */
adcifa_get_calibration_data(&AVR32_ADCIFA, &adc_config_t);
/* Calibrate offset first*/
adcifa_calibrate_offset(&AVR32_ADCIFA, &adc_config_t, sysclk_get_cpu_hz());
/* Configure ADCIFA core */
adcifa_configure(&AVR32_ADCIFA, &adc_config_t, sysclk_get_cpu_hz());
/* ADCIFA sequencer 0 configuration structure*/
adcifa_sequence_opt.convnb = EXAMPLE_ADCIFA_NUMBER_OF_SEQUENCE;
adcifa_sequence_opt.resolution = ADCIFA_SRES_12B;
adcifa_sequence_opt.trigger_selection = ADCIFA_TRGSEL_SOFT;
adcifa_sequence_opt.start_of_conversion = ADCIFA_SOCB_ALLSEQ;
adcifa_sequence_opt.sh_mode = ADCIFA_SH_MODE_OVERSAMP;
adcifa_sequence_opt.half_word_adjustment= ADCIFA_HWLA_NOADJ;
adcifa_sequence_opt.software_acknowledge= ADCIFA_SA_NO_EOS_SOFTACK;
/* ADCIFA conversions for sequencer 0*/
adcifa_sequence_conversion_opt[0].channel_p = EXAMPLE_ADC_POTENTIOMETER_INP;
adcifa_sequence_conversion_opt[0].channel_n = EXAMPLE_ADC_POTENTIOMETER_INN;
adcifa_sequence_conversion_opt[0].gain = ADCIFA_SHG_1;
adcifa_sequence_conversion_opt[1].channel_p = EXAMPLE_ADC_MIC_INP;
adcifa_sequence_conversion_opt[1].channel_n = EXAMPLE_ADC_MIC_INN;
adcifa_sequence_conversion_opt[1].gain = ADCIFA_SHG_8;
/* Window Monitor 0 Configuration */
/* Window Mode 2 -> Active (If Result Register > Low Threshold) */
adcifa_window_monitor_0_opt.mode = ADCIFA_WINDOW_MODE_ABOVE;
/* First channel in the configured sequence */
adcifa_window_monitor_0_opt.source_index = 0;
/* Low Threshold Equivalent ADC counts */
adcifa_window_monitor_0_opt.low_threshold = 0x1FF;
/* High Threshold Equivalent ADC counts */
adcifa_window_monitor_0_opt.high_threshold = 0;
/* Window Monitor 1 Configuration */
/* Window Mode 2 -> Active (If Result Register > Low Threshold) */
adcifa_window_monitor_1_opt.mode = ADCIFA_WINDOW_MODE_ABOVE;
/* Second channel in the configured sequence */
adcifa_window_monitor_1_opt.source_index = 1;
/* Low Threshold Equivalent ADC counts */
adcifa_window_monitor_1_opt.low_threshold = 0x1FF;
/* High Threshold Equivalent ADC counts */
adcifa_window_monitor_1_opt.high_threshold = 0;
/*
* Initialize the interrupt vectors
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_initialize_vectors();
/*
* Register the ADCIFA interrupt handler
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_register_handler(&ADCIFA_interrupt_handler, AVR32_ADCIFA_WINDOW_IRQ,
ADC_INTERRUPT_PRIORITY);
/* Enable global Interrupts */
Enable_global_interrupt();
/* Configure ADCIFA Window Monitor 0 */
adcifa_configure_window_monitor(&AVR32_ADCIFA, 0 ,
&adcifa_window_monitor_0_opt);
/* Configure ADCIFA Window Monitor 1 */
adcifa_configure_window_monitor(&AVR32_ADCIFA, 1 ,
&adcifa_window_monitor_1_opt);
/* Enable the Window Monitor 0 Interrupt */
adcifa_enable_interrupt(&AVR32_ADCIFA,AVR32_ADCIFA_IDR_WM0_MASK);
/* Enable the Window Monitor 1 Interrupt */
adcifa_enable_interrupt(&AVR32_ADCIFA,AVR32_ADCIFA_IDR_WM1_MASK);
/* Configure ADCIFA sequencer 0 */
adcifa_configure_sequencer(&AVR32_ADCIFA, 0, &adcifa_sequence_opt,
adcifa_sequence_conversion_opt);
/* Start ADCIFA sequencer 0 */
adcifa_start_sequencer(&AVR32_ADCIFA, 0);
while (true) {
/* Get Values from sequencer 0 */
if (adcifa_get_values_from_sequencer(&AVR32_ADCIFA, 0,
&adcifa_sequence_opt, adc_values) == ADCIFA_STATUS_COMPLETED) {
/* Display values to user */
/* Display header */
print_dbg("\x1B[2J\x1B[H\r\nADCIFA Example\r\n");
print_dbg("HEX Value for Channel potentiometer: 0x");
print_dbg_hex(adc_values[0]);
print_dbg("\r\n");
if(window1) {
/* Out of Range -> Action */
print_dbg(" Window 1 : Out of Range\r\n");
window1=false;
adcifa_enable_interrupt(&AVR32_ADCIFA,AVR32_ADCIFA_IDR_WM0_MASK);
} else {
print_dbg(" Window 1 : Inside Range\r\n");
}
print_dbg("HEX Value for Channel microphone: 0x");
print_dbg_hex(~adc_values[1]);
print_dbg("\r\n");
if(window2) {
/* Out of Range -> Action */
print_dbg(" Window 2 : Out of Range\r\n");
window2=false;
adcifa_enable_interrupt(&AVR32_ADCIFA,AVR32_ADCIFA_IDR_WM1_MASK);
} else {
print_dbg(" Window 2 : Inside Range\r\n");
}
/*
* Clear end-of-sequence for sequencer 0,
* ready for next conversion.
*/
ADCIFA_clear_eos_sequencer_0();
/* Start new ADCIFA sequencer 0 */
adcifa_start_sequencer(&AVR32_ADCIFA, 0);
}
/* Slow down display of converted values */
delay_ms(100);
}
}
/**
* \brief Main Application Routine
* - Initialize the system clocks
* - Initialize the sleep manager
* - Initialize the power save measures
* - Initialize the ADCIFB module
* - Initialize the AST to trigger ADCIFB at regular intervals
* - Go to STATIC sleep mode and wake up on a touch status change
*/
int main(void)
{
/* Switch on the STATUS LED */
gpio_clr_gpio_pin(STATUS_LED);
/* Switch off the error LED. */
gpio_set_gpio_pin(ERROR_LED);
/*
* Initialize the system clock.
* Note: Clock settings are specified in conf_clock.h
*/
sysclk_init();
/*
* Initialize the sleep manager.
* Note: CONFIG_SLEEPMGR_ENABLE should have been defined in conf_sleepmgr.h
*/
sleepmgr_init();
/* Lock required for sleep mode. */
sleepmgr_lock_mode(SLEEPMGR_STATIC);
/* Initialize the delay routines */
delay_init(sysclk_get_cpu_hz());
/* Initialize the power saving features */
power_save_measures_init();
#if DEBUG_MESSAGES
/* Enable the clock to USART interface */
sysclk_enable_peripheral_clock(DBG_USART);
/* Initialize the USART interface to print trace messages */
init_dbg_rs232(sysclk_get_pba_hz());
print_dbg("\r Sleepwalking with ADCIFB Module on UC3L \n");
print_dbg("\r Initializing ADCIFB Module..... \n");
#endif
/* Initialize the ADC peripheral */
if (adc_init() != STATUS_OK) {
#if DEBUG_MESSAGES
/* Error initializing the ADC peripheral */
print_dbg("\r Error initializing ADC module \n");
#endif
while (1) {
delay_ms(LED_DELAY);
gpio_tgl_gpio_pin(ERROR_LED);
}
}
#if DEBUG_MESSAGES
print_dbg("\r ADCIFB Module initialized. \n");
print_dbg("\r Initializing AST Module..... \n");
#endif
/* Initialize the AST peripheral */
if (ast_init() != STATUS_OK) {
#if DEBUG_MESSAGES
print_dbg("\r Error initializing AST module \n");
#endif
/* Error initializing the AST peripheral */
while (1) {
delay_ms(LED_DELAY);
gpio_tgl_gpio_pin(ERROR_LED);
}
}
#if DEBUG_MESSAGES
print_dbg("\r AST Module initialized. \n");
#endif
/* Application routine */
while (1) {
/* Enable Asynchronous wake-up for ADCIFB */
pm_asyn_wake_up_enable(AVR32_PM_AWEN_ADCIFBWEN_MASK);
#if DEBUG_MESSAGES
print_dbg("\r Going to STATIC sleep mode \n");
print_dbg(
"\r Wake up only when output is higher than threshold \n");
#endif
/* Switch off the status LED */
gpio_set_gpio_pin(STATUS_LED);
/* Disable GPIO clock before entering sleep mode */
sysclk_disable_pba_module(SYSCLK_GPIO);
AVR32_INTC.ipr[0];
/* Enter STATIC sleep mode */
sleepmgr_enter_sleep();
/* Enable GPIO clock after waking from sleep mode */
sysclk_enable_pba_module(SYSCLK_GPIO);
/* Switch on the status LED */
gpio_clr_gpio_pin(STATUS_LED);
#if DEBUG_MESSAGES
print_dbg("\r Output higher than threshold \n");
print_dbg("\r ADC Output : 0x");
print_dbg_hex(adc_output);
print_dbg("\n");
#else
/* LED on for few ms */
delay_ms(LED_DELAY);
#endif
/* Clear the wake up & enable it to enter sleep mode again */
pm_asyn_wake_up_disable(AVR32_PM_AWEN_ADCIFBWEN_MASK);
/* Clear All AST Interrupt request and clear SR */
ast_clear_all_status_flags(&AVR32_AST);
}
return 0;
} /* End of main() */
// main function
int main(void)
{
bool valid_block_found[NF_N_DEVICES];
U32 u32_nf_ids, i_dev, i_block;
U8 maker_id, device_id;
U32 i, j;
// ECCHRS options.
static const ecchrs_options_t ECCHRS_OPTIONS =
{
.typecorrect = ECCHRS_TYPECORRECT_4_BIT,
.pagesize = ECCHRS_PAGESIZE_4_BIT_2112_W
};
// switch to oscillator 0
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
// init debug serial interface
init_dbg_rs232(FOSC0);
nf_init(FOSC0); // init the nand flash driver with the correct HSB frequency
nf_unprotect();
print_dbg("\r\nECCHRS example using Nand Flash.\r\n================================\r\n\r\n");
// - Simple test of the NF communication through the SMC.
// - Find all bad blocks.
// - Find a valid block for the remaining tests.
nf_reset_nands(NF_N_DEVICES);
print_dbg("\tCPU, HSB is at 12000000Mhz.\r\n");
print_dbg("\tPBA, PBB is at 12000000Mhz.\r\n");
print_dbg("\tDetecting Nand Flash device(s).\r\n");
for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ )
{
// Performs some init here...
valid_block_found[i_dev] = false;
// Test Maker and Device ids
u32_nf_ids = nf_read_id( NF_READ_ID_CMD, i_dev );
maker_id = MSB0(u32_nf_ids);
device_id = MSB1(u32_nf_ids);
print_dbg("\t\tNF");
print_dbg_hex(i_dev);
print_dbg(" [Maker=");
print_dbg_hex(maker_id);
print_dbg("] [Device=");
print_dbg_hex(device_id);
print_dbg("]\r\n");
if( maker_id==M_ID_MICRON )
{
print_dbg("\t\t Micron chip");
if( device_id==0xDA ){
print_dbg("- MT29F2G08AACWP device\r\n");
}
else
{
print_dbg("- *** Error: unexpected chip detected. Please check the board settings and hardware.\r\n");
return -1;
}
}
else
{
print_dbg("\t\t *** Error: unexpected chip detected. Please check the board settings and hardware.\r\n");
return -1;
}
}
// Looking for valid blocks for the test.
for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ )
{
nf_select(i_dev);
for( i_block=0 ; i_block<G_N_BLOCKS ; i_block++ )
{
nf_open_page_read( nf_block_2_page(i_block), NF_SPARE_POS + G_OFST_BLK_STATUS );
if( (nf_rd_data()==0xFF) )
{ // The block is valid.
print_dbg("\tValid block found (");
print_dbg_ulong(i_block);
print_dbg(") on NF ");
print_dbg_hex(i_dev);
print_dbg("\r\n");
valid_block_found[i_dev]= true;
valid_block_addr[i_dev] = i_block;
break;
}
}
}
for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ )
if( !valid_block_found[i_dev] )
{
print_dbg("Error: no valid blocks found.\r\n");
return 0;
}
print_dbg("\tECCHRS IP ver ");
print_dbg_ulong(ecchrs->version);
print_dbg("(");
print_dbg_hex(ecchrs->version);
print_dbg(")");
print_dbg("\r\n");
// Work with NF 0 from now...
nf_select(0);
// Setup the ECCHRS.
ecchrs_init(&AVR32_ECCHRS, &ECCHRS_OPTIONS);
// Ensures that the block is erased for the test.
print_dbg("\tErasing a free block for the test.\r\n");
nf_erase_block(nf_block_2_page(valid_block_addr[0]), false);
// Reset the ECCHRS state machine.
ecchrs_reset(&AVR32_ECCHRS);
// Program a simple patterns in the first page.
print_dbg("\tProgramming the first page with a simple pattern.\r\n");
nf_open_page_write( nf_block_2_page(valid_block_addr[0]), 0);
for ( i = 0; i < 2048/2; i++ )
{
U16 val = i;
nf_wr_data(MSB(val));
nf_wr_data(LSB(val));
}
// Extract the ECCs and store them at the end of the page.
// [2054; 2063]: codeword 0:9
// [2070; 2079]: codeword 10:19
// [2086; 2095]: codeword 20:29
// [2102; 2111]: codeword 30:39
// Since we use the Random Data Output command, we need to freeze
// the ECCHRS in order to keep our ECC codewords unchanged.
print_dbg("\tExtracting the ECCHRS codewords and store them in the page.\r\n");
ecchrs_freeze(&AVR32_ECCHRS); // not needed if ECCHRS reaches the end of page.
for ( i=0 ; i<4 ; i++ )
{
U16 offset = 2048+6+16*i;
nf_wr_cmd(NF_RANDOM_DATA_INPUT_CMD);
nf_wr_addr( LSB(offset) );
nf_wr_addr( MSB(offset) );
for ( j=0 ; j<10 ; j++ )
nf_wr_data( ecchrs_get_cw(&AVR32_ECCHRS, i*10+j) );
}
ecchrs_unfreeze(&AVR32_ECCHRS);
nf_wr_cmd(NF_PAGE_PROGRAM_CMD);
// Now let's test the ECC verification.
print_dbg("\tReading the first page.\r\n");
nf_open_page_read( nf_block_2_page(valid_block_addr[0]), 0);
for( i=0 ; i<2048 ; i++ )
nf_rd_data();
print_dbg("\tChecking if the data are valid thanks to the ECCHRS codewords.\r\n");
for ( i=0 ; i<4 ; i++ )
{
U16 offset = 2048+6+16*i;
ecchrs_freeze(&AVR32_ECCHRS);
nf_wr_cmd(NF_RANDOM_READ_CMD_C1);
nf_wr_addr( LSB(offset) );
nf_wr_addr( MSB(offset) );
nf_wr_cmd(NF_RANDOM_READ_CMD_C2);
ecchrs_unfreeze(&AVR32_ECCHRS);
for ( j=0 ; j<10 ; j++ )
nf_rd_data();
}
// Check if there is any errors after the read of the page.
i = ecchrs_4bit_check_error(&AVR32_ECCHRS);
print_dbg("\tSR1 is ");
print_dbg_ulong(i);
print_dbg("(");
print_dbg_hex(i);
print_dbg(")");
print_dbg("\r\n");
if(i&(15))
{
print_dbg("\tERROR: ECCHRS detects some errors in the sectors 1, 2, 3 or 4\r\n");
}
else
print_dbg("\tNo error detected.\r\n");
// Let the block free.
nf_erase_block(nf_block_2_page(valid_block_addr[0]), false);
return 0;
}
// query the blackfin for parameter list and populate pnodes
u8 net_report_params(void) {
volatile char buf[64];
volatile ParamDesc pdesc;
volatile u32 numParams;
s32 val;
u8 i;
bfin_get_num_params(&numParams);
print_dbg("\r\nnumparams: ");
print_dbg_ulong(numParams);
if(numParams == 255) {
print_dbg("\r\n report_params fail (255)");
return 0;
}
if(numParams > 0) {
net_clear_params();
for(i=0; i<numParams; i++) {
///////
///////
// TODO: offline param descriptor
bfin_get_param_desc(i, &pdesc);
///////
/////
print_dbg("\r\n received descriptor for param, index : ");
print_dbg_ulong(i);
print_dbg(" , label : ");
print_dbg((const char* )pdesc.label);
print_dbg(" ; \t initial value: 0x");
val = bfin_get_param(i);
print_dbg_hex(val);
net_add_param(i, (const ParamDesc*)&pdesc);
print_dbg("\r\n finished adding parameter.");
// net->params[net->numParams - 1].data.value = val;
//// use reverse-lookup method from scaler
net->params[net->numParams - 1].data.value =
scaler_get_in( &(net->params[net->numParams - 1].scaler), val);
net->params[net->numParams - 1].data.changed = 0;
}
} else {
print_dbg("\r\n bfin: no parameters reported");
return 0;
}
delay_ms(100);
print_dbg("\r\n checking module label ");
bfin_get_module_name(buf);
delay_ms(10);
print_dbg("\r\n bfin module name: ");
print_dbg((const char*)buf);
// if(numParams > 0 && numParams != 255) {
/// test bfin_get_param on initial values
// print_dbg("\r\n reporting inital param values: ");
// for(i=0; i<numParams; ++i) {
// print_dbg("\r\n 0x");
// val = bfin_get_param(i);
// print_dbg_hex(val);
// }
// }
return (u8)numParams;
}
// scroll the current selection
static void select_scroll(s32 dir) {
const s32 max = net_num_ins() - 1;
// index for new content
s16 newIdx;
s16 newSel;
s16 oldSel;
int i;
// wrap with blank line
newSel = *pageSelect + dir;
if (newSel < -1) {
newSel += (max + 2);
}
if(newSel > max) {
newSel -= (max + 2);
}
print_dbg("\r\n scrolled selection on inputs page, old sel: ");
print_dbg_ulong(*pageSelect);
print_dbg(" , dir: ");
print_dbg_hex(dir);
print_dbg(" , new idx: ");
print_dbg_ulong(newSel);
oldSel = *pageSelect;
*pageSelect = newSel;
// remove highlight from old center
render_scroll_apply_hl(SCROLL_CENTER_LINE, 0);
// update 'zeroed' flag
zeroed = (net_get_in_value(*pageSelect) == 0);
if(dir > 0) {
// add content at bottom
for(i=0; i<dir; ++i) {
newIdx = oldSel + SCROLL_LINES_BELOW + i + 2;
if(newIdx == (max + 1)) {
region_fill(lineRegion, 0);
} else {
if(newIdx > max) {
newIdx = newIdx - (max+2);
}
print_dbg(" , rendering new line for idx: ");
print_dbg_ulong(newIdx);
render_line(newIdx, 0xa);
}
// render tmp region to bottom of scroll
// (this also updates scroll byte offset)
render_to_scroll_bottom();
// add highlight to new center
}
render_scroll_apply_hl(SCROLL_CENTER_LINE, 1);
} else {
// add content at top
for(i=0; i>dir; --i) {
newIdx = oldSel - SCROLL_LINES_ABOVE + i;
if(newIdx == -1) {
region_fill(lineRegion, 0);
} else {
if(newIdx < -1) {
newIdx = newIdx + max + 2;
}
print_dbg(" , rendering new line for idx: ");
print_dbg_ulong(newIdx);
render_line(newIdx, 0xa);
}
// render tmp region to top of scroll
// (this also updates scroll byte offset)
render_to_scroll_top();
}
// add highlight to new center
render_scroll_apply_hl(SCROLL_CENTER_LINE, 1);
}
}
// app event loop
static void check_events(void) {
static event_t e;
// u8 launch = 0;
// print_dbg("\r\n checking events...");
if( get_next_event(&e) ) {
/* print_dbg("\r\n handling event, type: "); */
/* print_dbg_hex(e.eventType); */
/* print_dbg("\r\n , data: "); */
/* print_dbg_hex(e.eventData); */
if(startup) {
if( e.eventType == kEventSwitch0
|| e.eventType == kEventSwitch1
|| e.eventType == kEventSwitch2
|| e.eventType == kEventSwitch3
|| e.eventType == kEventSwitch4
) {
startup = 0;
print_dbg("\r\n key pressed, launching ");
// return 1 if app completed firstrun tasks
// launch = app_launch(firstrun);
delay_ms(10);
if( firstrun) {
// if(launch) {
// successfully launched on firstrun, so write magic number to flash
flash_write_firstrun();
// return;
// } else {
// firstrun, but app launch failed, so clear magic number to try again
// flash_clear_firstrun();
// }
}
}
} else {
switch(e.eventType) {
case kEventRefresh:
// refresh the screen hardware
// screen_refresh();
/// draw ADC values
break;
case kEventMonomePoll :
// poll monome serial input and spawn relevant events
monome_read_serial();
break;
case kEventMonomeRefresh :
// refresh monome device from led state buffer
monome_grid_refresh();
break;
//--------------------------------------
case kEventFtdiConnect:
// perform setup tasks for new ftdi device connection.
// won't work if called from an interrupt.
ftdi_setup();
break;
case kEventFtdiDisconnect:
break;
case kEventHidConnect :
break;
case kEventHidDisconnect :
break;
case kEventMidiConnect :
break;
case kEventMidiDisconnect :
break;
case kEventEncoder0 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventEncoder0");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
dac_inc(0, scale_knob_value(e.eventData));
break;
case kEventEncoder1 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventEncoder1");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
dac_inc(1, scale_knob_value(e.eventData));
break;
case kEventEncoder2 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventEncoder2");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
dac_inc(2, scale_knob_value(e.eventData));
break;
case kEventEncoder3 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventEncoder3");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
dac_inc(3, scale_knob_value(e.eventData));
break;
case kEventSwitch0 : // fn
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch0");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch1 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch1");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch2 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch2");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch3 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch3");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch4 : // mode
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch4");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch5 : // power
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch5");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch6 : // foot
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch6");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventSwitch7 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventSwitch7");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventAdc0 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventAdc0");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventAdc1 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventAdc1");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventAdc2 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventAdc2");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventAdc3 :
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventAdc3");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
break;
case kEventMonomeGridKey:
print_dbg("\r\n ( 0x"); print_dbg_hex((u32)tcTicks); print_dbg(" ) kEventMonomeGridKey");
print_dbg(" : 0x"); print_dbg_hex((u32) e.eventData);
handle_monome_grid_key((u32)e.eventData);
break;
default:
// (*appEventHandler)(&e);
break;
} // event switch
} // startup
} // got event
}
// malloc() tests
void test_malloc( void )
{
//##################################################
//## II. Dynamic allocation in external SDRAM tests.
//##################################################
int *pBuf; // Pointer on malloc'ed buffer
int *pTempo; // Temporary pointer
int i,j; // counters.
int iTempoValue; // Temporary value
U8 u8NbErrors = 0; // Number of read/write errors
int *au32StoreMallocPtr[EXTSDRAM_EXAMPLE_NB_MALLOC];
for(i=0; i<EXTSDRAM_EXAMPLE_NB_MALLOC; i++)
{
// II.1 Malloc a buffer of EXTSDRAM_EXAMPLE_MALLOC_SIZE int.
pBuf = (int *)malloc(EXTSDRAM_EXAMPLE_MALLOC_SIZE*sizeof(int));
au32StoreMallocPtr[i] = pBuf;
if (pBuf)
{ // Malloc succeeded.
// Print the address of the allocated buffer to USART1.
print_dbg("\r\nMalloc OK at address: 0x");
print_dbg_hex((int) pBuf);
// II.2 Fill this buffer with a pattern.
print_dbg("\r\nWriting the pattern 0x");
print_dbg_hex(EXTSDRAM_EXAMPLE_PATTERN);
print_dbg(" to the dynamically allocated buffer...");
pTempo = pBuf;
j = EXTSDRAM_EXAMPLE_MALLOC_SIZE;
while(j--)
*pTempo++ = EXTSDRAM_EXAMPLE_PATTERN;
// II.3 Check that the pattern was correctly written.
print_dbg("\r\nChecking...");
u8NbErrors = 0;
pTempo--;
while(pTempo >= pBuf)
{
iTempoValue = *pTempo--;
if(EXTSDRAM_EXAMPLE_PATTERN != iTempoValue)
{
u8NbErrors++;
print_dbg("\r\nInvalid value read: 0x");
print_dbg_hex(iTempoValue);
}
}
print_dbg("\r\nNumber of read/write errors: ");
print_dbg_ulong(u8NbErrors);
print_dbg("\r\n");
}
else
{ // Should never happen!
print_dbg("\r\nMalloc failed\r\n");
}
}
// II.4 Free the previously allocated buffers.
for(i=0; i<EXTSDRAM_EXAMPLE_NB_MALLOC; i++)
{
pBuf = au32StoreMallocPtr[i];
if(NULL != pBuf)
free(pBuf);
}
}
/** \brief Main application entry point - init and loop to display ADC values */
int main(void)
{
#if defined(EXAMPLE_ADC_TEMPERATURE_CHANNEL)
signed short adc_value_temp = -1;
#endif
#if defined(EXAMPLE_ADC_LIGHT_CHANNEL)
signed short adc_value_light = -1;
#endif
#if defined(EXAMPLE_ADC_POTENTIOMETER_CHANNEL)
signed short adc_value_pot = -1;
#endif
/* Init system clocks */
sysclk_init();
/* init debug serial line */
init_dbg_rs232(sysclk_get_cpu_hz());
/* Assign and enable GPIO pins to the ADC function. */
gpio_enable_module(ADC_GPIO_MAP, sizeof(ADC_GPIO_MAP) /
sizeof(ADC_GPIO_MAP[0]));
/* Configure the ADC peripheral module.
* Lower the ADC clock to match the ADC characteristics (because we
* configured the CPU clock to 12MHz, and the ADC clock characteristics are
* usually lower; cf. the ADC Characteristic section in the datasheet). */
AVR32_ADC.mr |= 0x1 << AVR32_ADC_MR_PRESCAL_OFFSET;
adc_configure(&AVR32_ADC);
/* Enable the ADC channels. */
#if defined(EXAMPLE_ADC_TEMPERATURE_CHANNEL)
adc_enable(&AVR32_ADC, EXAMPLE_ADC_TEMPERATURE_CHANNEL);
#endif
#if defined(EXAMPLE_ADC_LIGHT_CHANNEL)
adc_enable(&AVR32_ADC, EXAMPLE_ADC_LIGHT_CHANNEL);
#endif
#if defined(EXAMPLE_ADC_POTENTIOMETER_CHANNEL)
adc_enable(&AVR32_ADC, EXAMPLE_ADC_POTENTIOMETER_CHANNEL);
#endif
/* Display a header to user */
print_dbg("\x1B[2J\x1B[H\r\nADC Example\r\n");
while (true) {
/* Start conversions on all enabled channels */
adc_start(&AVR32_ADC);
#if defined(EXAMPLE_ADC_TEMPERATURE_CHANNEL)
/* Get value for the temperature adc channel */
adc_value_temp = adc_get_value(&AVR32_ADC,
EXAMPLE_ADC_TEMPERATURE_CHANNEL);
/* Display value to user */
print_dbg("HEX Value for Channel temperature : 0x");
print_dbg_hex(adc_value_temp);
print_dbg("\r\n");
#endif
#if defined(EXAMPLE_ADC_LIGHT_CHANNEL)
/* Get value for the light adc channel */
adc_value_light = adc_get_value(&AVR32_ADC,
EXAMPLE_ADC_LIGHT_CHANNEL);
/* Display value to user */
print_dbg("HEX Value for Channel light : 0x");
print_dbg_hex(adc_value_light);
print_dbg("\r\n");
#endif
#if defined(EXAMPLE_ADC_POTENTIOMETER_CHANNEL)
/* Get value for the potentiometer adc channel */
adc_value_pot = adc_get_value(&AVR32_ADC,
EXAMPLE_ADC_POTENTIOMETER_CHANNEL);
/* Display value to user */
print_dbg("HEX Value for Channel pot : 0x");
print_dbg_hex(adc_value_pot);
print_dbg("\r\n");
#endif
/* Slow down the display of converted values */
delay_ms(500);
}
return 0;
}
// fill global RAM buffer with current state of system
void scene_write_buf(void) {
u8* dst = (u8*)(sceneData->pickle);
char test[SCENE_NAME_LEN] = " ";
u32 bytes = 0;
u8* newDst = NULL;
int i;
///// print paramameters
// u32 i;
print_dbg("\r\n writing scene data... ");
/* for(i=0; i<net->numParams; i++) {
print_dbg("\r\n param ");
print_dbg_ulong(i);
print_dbg(" : ");
print_dbg(net->params[i].desc.label);
print_dbg(" ; val ");
print_dbg_hex((u32)net->params[i].data.value.asInt);
}
*/
// write name
for(i=0; i<SCENE_NAME_LEN; i++) {
*dst = sceneData->desc.sceneName[i];
dst++;
bytes++;
}
// write bees version
*dst = sceneData->desc.beesVersion.min;
dst++; bytes++;
*dst = sceneData->desc.beesVersion.maj;
dst++; bytes++;
dst = pickle_16(sceneData->desc.beesVersion.rev, dst);
bytes += 2;
print_dbg("\r\n scene_write buf; module name: ");
print_dbg(sceneData->desc.moduleName);
// write module name
for(i=0; i<MODULE_NAME_LEN; i++) {
*dst = (sceneData->desc.moduleName)[i];
dst++;
bytes++;
}
//// TEST
for(i=0; i<MODULE_NAME_LEN; i++) {
test[i] = *(dst - MODULE_NAME_LEN + i);
}
print_dbg("; test buffer after write: ");
print_dbg(test);
////
// write module version
*dst = sceneData->desc.moduleVersion.min;
dst++;
*dst = sceneData->desc.moduleVersion.maj;
dst++;
dst = pickle_16(sceneData->desc.moduleVersion.rev, dst);
bytes += 4;
// pickle network
newDst = net_pickle(dst);
bytes += (newDst - dst);
print_dbg("\r\n pickled network, bytes written: 0x");
print_dbg_hex(bytes);
dst = newDst;
// pickle presets
newDst = presets_pickle(dst);
bytes += (newDst - dst);
print_dbg("\r\n pickled presets, bytes written: 0x");
print_dbg_hex(bytes);
dst = newDst;
#if RELEASEBUILD==1
#else
if(bytes > SCENE_PICKLE_SIZE - 0x800) {
print_dbg(" !!!!!!!! warning: serialized scene data approaching allocated bounds !!!!! ");
}
if(bytes > SCENE_PICKLE_SIZE) {
print_dbg(" !!!!!!!! error: serialized scene data exceeded allocated bounds !!!!! ");
}
#endif
}
