static void
clockreset(Timerregs *tn)
{
if (probeaddr((uintptr)&tn->ticpcfg) < 0)
panic("no clock at %#p", tn);
tn->ticpcfg = Softreset | Noidle;
coherence();
resetwait(tn);
tn->tier = tn->tclr = 0;
coherence();
}
static int
gotmem(uintptr sz)
{
uintptr addr;
addr = PHYSDRAM + sz - MB;
mmuidmap(addr, 1);
if (probeaddr(addr) >= 0) {
memsize = sz;
return 0;
}
return -1;
}
static void
spiprobe(void)
{
if (0) {
/* generates repeated "spurious irqbridge interrupt: 00000010" on sheevaplug. */
Spiregs *rp = (Spiregs *)soc.spi;
if (probeaddr(soc.spi) < 0)
return;
rp->ictl |= Csnact;
coherence();
rp->icfg |= Dirrdcmd | 3<<8; /* fast reads, 4-byte addresses */
rp->icfg &= ~Bytelen; /* one-byte reads */
coherence();
print("spi flash ignored: ctlr %#p, data %#ux", rp, PHYSSPIFLASH);
mmuidmap(PHYSSPIFLASH, 1);
if (probeaddr(PHYSSPIFLASH) < 0)
print(" (no response)");
print(": memory reads enabled\n");
}
}
void
dmainit(void)
{
int n;
char name[16];
Dchan *cp;
Regs *regs = (Regs *)PHYSSDMA;
if (probeaddr((uintptr)®s->syssts) < 0)
panic("dmainit: no syssts reg");
regs->syssts = 0;
coherence();
regs->syscfg |= 1<<1; /* Softreset */
coherence();
while(!(regs->syssts & (1<<0))) /* Resetdone? */
;
for (n = 0; n < Nchan; n++) {
cp = regs->chan + n;
cp->ccr = 0;
cp->clnkctrl = 0;
cp->cicr = 0;
cp->csr = 0;
cp->csdp = 0;
cp->cen = cp->cfn = 0;
cp->cssa = cp->cdsa = 0;
cp->csei = cp->csfi = 0;
cp->cdei = cp->cdfi = 0;
// cp->csac = cp->cdac = 0; // ro
cp->ccen = cp->ccfn = 0;
cp->color = 0;
}
zerowds((void *)regs->irqsts, sizeof regs->irqsts / sizeof(ulong));
zerowds((void *)regs->irqen, sizeof regs->irqen / sizeof(ulong));
coherence();
regs->gcr = 65; /* burst size + 1 */
coherence();
for (n = 0; n < Nirq; n++) {
snprint(name, sizeof name, "dma%d", n);
intrenable(Baseirq + n, dmaintr, (void *)n, nil, name);
}
}
static void
missing(ulong addr, char *name)
{
static int firstmiss = 1;
if (addr == 0) {
iprint("address zero for %s\n", name);
return;
}
if (probeaddr(addr) >= 0)
return;
missed++;
if (firstmiss) {
iprint("missing:");
firstmiss = 0;
} else
iprint(",\n\t");
iprint(" %s at %#lux", name, addr);
}
static int
reset(Hci *hp)
{
Ctlr *ctlr;
Ecapio *capio;
Eopio *opio;
Uhh *uhh;
static int beenhere;
if (beenhere)
return -1;
beenhere = 1;
if(getconf("*nousbehci") != nil || probeaddr(PHYSEHCI) < 0)
return -1;
ctlr = smalloc(sizeof(Ctlr));
/*
* don't bother with vmap; i/o space is all mapped anyway,
* and a size less than 1MB will blow an assertion in mmukmap.
*/
ctlr->capio = capio = (Ecapio *)PHYSEHCI;
ctlr->opio = opio = (Eopio*)((uintptr)capio + (capio->cap & 0xff));
hp->aux = ctlr;
hp->port = (uintptr)ctlr->capio;
hp->irq = 77;
hp->nports = capio->parms & Cnports;
ddprint("echi: %s, ncc %lud npcc %lud\n",
capio->parms & 0x10000 ? "leds" : "no leds",
(capio->parms >> 12) & 0xf, (capio->parms >> 8) & 0xf);
ddprint("ehci: routing %s, %sport power ctl, %d ports\n",
capio->parms & 0x40 ? "explicit" : "automatic",
capio->parms & 0x10 ? "" : "no ", hp->nports);
ehcireset(ctlr);
ehcimeminit(ctlr);
/* omap35-specific set up */
/* bit 5 `must be set to 1 for proper behavior', spruf98d §23.2.6.7.17 */
opio->insn[4] |= 1<<5;
coherence();
/* insn[5] is for both utmi and ulpi, depending on hostconfig mode */
uhh = (Uhh *)PHYSUHH;
if (uhh->hostconfig & P1ulpi_bypass) { /* utmi port 1 active */
/* not doing this */
iprint("usbehci: bypassing ulpi on port 1!\n");
opio->insn[5] &= ~(MASK(4) << 13);
opio->insn[5] |= 1 << 13; /* select port 1 */
coherence();
} else { /* ulpi port 1 active */
/* TODO may need to reset gpio port2 here */
/* disable integrated stp pull-up resistor */
wrulpi(opio, 1, Ifcctlreg, Phystppullupoff);
/* force phy to `high-speed' */
wrulpi(opio, 1, Funcctlreg, 0x40);
}
/*
* Linkage to the generic HCI driver.
*/
ehcilinkage(hp);
hp->shutdown = shutdown;
hp->debug = setdebug;
intrenable(78, hp->interrupt, hp, UNKNOWN, "usbtll");
intrenable(92, hp->interrupt, hp, UNKNOWN, "usb otg");
intrenable(93, hp->interrupt, hp, UNKNOWN, "usb otg dma");
return 0;
}
