void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct) { print_tx("dct: ", dct); print_tx("Speed: ", pDCTstat->Speed); Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed, pDCTstat->MAload[dct], pDCTstat->DATAload[dct], &(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]), &pDCTstat->_2Tmode); if (pDCTstat->MAdimms[dct] == 1) pDCTstat->CH_ODC_CTL[dct] |= 0x20000000; /* 75ohms */ else pDCTstat->CH_ODC_CTL[dct] |= 0x10000000; /* 150ohms */ /* * Overrides and/or workarounds */ pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]); print_tx("4 CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); print_tx("4 CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); }
} } else { val &= valx; if (val != 0) { if (pDCTstat->Speed == 3 || pDCTstat->Speed == 3) { pDCTstat->CH_ADDR_TMG[dct] &= 0xFFFF00FF; pDCTstat->CH_ADDR_TMG[dct] |= 0x00002F00; } } } } } pDCTstat->CH_ODC_CTL[dct] = procOdtWorkaround(pDCTstat, dct, pDCTstat->CH_ODC_CTL[dct]); print_tx("CH_ODC_CTL: ", pDCTstat->CH_ODC_CTL[dct]); print_tx("CH_ADDR_TMG: ", pDCTstat->CH_ADDR_TMG[dct]); } /*=============================================================================== * Vendor is responsible for correct settings. * M2/Unbuffered 4 Slot - AMD Design Guideline. *=============================================================================== * #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key) * #2, BYTE, number of Address bus loads on the Channel. (Tershery Key) * These must be listed in ascending order.