static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
uint32_t val;
if (is_a64(env)) {
val = pstate_read(env);
} else {
val = cpsr_read(env);
}
qemu_put_be32(f, val);
}
int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
#ifndef CONFIG_USER_ONLY
if (!is_a64(env)) {
map_a32_to_a64_regs(env);
}
#endif
if (n < 31) {
/* Core integer register. */
return gdb_get_reg64(mem_buf, env->xregs[n]);
}
switch (n) {
case 31:
{
unsigned int cur_el = arm_current_el(env);
uint64_t sp;
aarch64_save_sp(env, cur_el);
switch (env->debug_ctx) {
case DEBUG_EL0:
sp = env->sp_el[0];
break;
case DEBUG_EL1:
sp = env->sp_el[1];
break;
case DEBUG_EL2:
sp = env->sp_el[2];
break;
case DEBUG_EL3:
sp = env->sp_el[3];
break;
default:
sp = env->xregs[31];
break;
}
return gdb_get_reg64(mem_buf, sp);
}
case 32:
return gdb_get_reg64(mem_buf, env->pc);
case 33:
return gdb_get_reg32(mem_buf, pstate_read(env));
}
/* Unknown register. */
return 0;
}
int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
{
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
if (n < 31) {
/* Core integer register. */
return gdb_get_reg64(mem_buf, env->xregs[n]);
}
switch (n) {
case 31:
return gdb_get_reg64(mem_buf, env->xregs[31]);
case 32:
return gdb_get_reg64(mem_buf, env->pc);
case 33:
return gdb_get_reg32(mem_buf, pstate_read(env));
}
/* Unknown register. */
return 0;
}
