static int xilinx_timer_init(SysBusDevice *dev)
{
struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
unsigned int i;
/* All timers share a single irq line. */
sysbus_init_irq(dev, &t->irq);
/* Init all the ptimers. */
t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
for (i = 0; i < num_timers(t); i++) {
struct xlx_timer *xt = &t->timers[i];
xt->parent = t;
xt->nr = i;
xt->bh = qemu_bh_new(timer_hit, xt);
xt->ptimer = ptimer_init(xt->bh);
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
memory_region_init_io(&t->mmio, &timer_ops, t, "xlnx.xps-timer",
R_MAX * 4 * num_timers(t));
sysbus_init_mmio(dev, &t->mmio);
return 0;
}
static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
{
sh_timer_state *s;
QEMUBH *bh;
s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
s->freq = freq;
s->feat = feat;
s->tcor = 0xffffffff;
s->tcnt = 0xffffffff;
s->tcpr = 0xdeadbeef;
s->tcr = 0;
s->enabled = 0;
s->irq = irq;
bh = qemu_bh_new(sh_timer_tick, s);
s->timer = ptimer_init(bh);
sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
/* ??? Save/restore. */
return s;
}
static int grlib_gptimer_init(SysBusDevice *dev)
{
GPTimerUnit *unit = FROM_SYSBUS(typeof(*unit), dev);
unsigned int i;
assert(unit->nr_timers > 0);
assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
for (i = 0; i < unit->nr_timers; i++) {
GPTimer *timer = &unit->timers[i];
timer->unit = unit;
timer->bh = qemu_bh_new(grlib_gptimer_hit, timer);
timer->ptimer = ptimer_init(timer->bh);
timer->id = i;
/* One IRQ line for each timer */
sysbus_init_irq(dev, &timer->irq);
ptimer_set_freq(timer->ptimer, unit->freq_hz);
}
memory_region_init_io(&unit->iomem, &grlib_gptimer_ops, unit, "gptimer",
UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
sysbus_init_mmio(dev, &unit->iomem);
return 0;
}
/** Gets the number of milliseconds or microseconds elapsed since given timer
* initialization
* @param timer an initialized timer
* @param prec the precision to get, from PTIMER_SEC to PTIMER_USEC
* @return The number of milliseconds or microseconds since timer initialization
*/
unsigned long ptimer_get_elapsed (const PTimer* timer, long prec)
{
PTimer ctimer;
ptimer_init (&ctimer);
return ptimer_diff (timer, &ctimer, prec);
}
static void imx_epit_realize(DeviceState *dev, Error **errp)
{
IMXEPITState *s = IMX_EPIT(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
QEMUBH *bh;
DPRINTF("\n");
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
0x00001000);
sysbus_init_mmio(sbd, &s->iomem);
s->timer_reload = ptimer_init(NULL);
bh = qemu_bh_new(imx_epit_cmp, s);
s->timer_cmp = ptimer_init(bh);
}
static int etraxfs_timer_init(SysBusDevice *dev)
{
struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
t->bh_t0 = qemu_bh_new(timer0_hit, t);
t->bh_t1 = qemu_bh_new(timer1_hit, t);
t->bh_wd = qemu_bh_new(watchdog_hit, t);
t->ptimer_t0 = ptimer_init(t->bh_t0);
t->ptimer_t1 = ptimer_init(t->bh_t1);
t->ptimer_wd = ptimer_init(t->bh_wd);
sysbus_init_irq(dev, &t->irq);
sysbus_init_irq(dev, &t->nmi);
memory_region_init_io(&t->mmio, &timer_ops, t, "etraxfs-timer", 0x5c);
sysbus_init_mmio(dev, &t->mmio);
qemu_register_reset(etraxfs_timer_reset, t);
return 0;
}
static int marin_timer_init(SysBusDevice *dev)
{
MarinTimerState *s = MARIN_TIMER(dev);
sysbus_init_irq(dev, &s->irq);
s->bh = qemu_bh_new(marin_timer_tick, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
return 0;
}
static int milkymist_sysctl_init(SysBusDevice *dev)
{
MilkymistSysctlState *s = FROM_SYSBUS(typeof(*s), dev);
sysbus_init_irq(dev, &s->gpio_irq);
sysbus_init_irq(dev, &s->timer0_irq);
sysbus_init_irq(dev, &s->timer1_irq);
s->bh0 = qemu_bh_new(timer0_hit, s);
s->bh1 = qemu_bh_new(timer1_hit, s);
s->ptimer0 = ptimer_init(s->bh0);
s->ptimer1 = ptimer_init(s->bh1);
ptimer_set_freq(s->ptimer0, s->freq_hz);
ptimer_set_freq(s->ptimer1, s->freq_hz);
memory_region_init_io(&s->regs_region, &sysctl_mmio_ops, s,
"milkymist-sysctl", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}
static int etraxfs_timer_init(SysBusDevice *dev)
{
struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
int timer_regs;
t->bh_t0 = qemu_bh_new(timer0_hit, t);
t->bh_t1 = qemu_bh_new(timer1_hit, t);
t->bh_wd = qemu_bh_new(watchdog_hit, t);
t->ptimer_t0 = ptimer_init(t->bh_t0);
t->ptimer_t1 = ptimer_init(t->bh_t1);
t->ptimer_wd = ptimer_init(t->bh_wd);
sysbus_init_irq(dev, &t->irq);
sysbus_init_irq(dev, &t->nmi);
timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, t);
return 0;
}
static void etsec_realize(DeviceState *dev, Error **errp)
{
eTSEC *etsec = ETSEC_COMMON(dev);
etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
object_get_typename(OBJECT(dev)), dev->id, etsec);
qemu_format_nic_info_str(qemu_get_queue(etsec->nic), etsec->conf.macaddr.a);
etsec->bh = qemu_bh_new(etsec_timer_hit, etsec);
etsec->ptimer = ptimer_init(etsec->bh, PTIMER_POLICY_DEFAULT);
ptimer_set_freq(etsec->ptimer, 100);
}
static arm_timer_state *arm_timer_init(uint32_t freq)
{
arm_timer_state *s;
QEMUBH *bh;
s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
s->freq = freq;
s->control = TIMER_CTRL_IE;
bh = qemu_bh_new(arm_timer_tick, s);
s->timer = ptimer_init(bh);
vmstate_register(NULL, -1, &vmstate_arm_timer, s);
return s;
}
static arm_timer_state *arm_timer_init(uint32_t freq)
{
arm_timer_state *s;
QEMUBH *bh;
s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
s->freq = freq;
s->control = TIMER_CTRL_IE;
bh = qemu_bh_new(arm_timer_tick, s);
s->timer = ptimer_init(bh);
register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
return s;
}
static void imx_gpt_realize(DeviceState *dev, Error **errp)
{
IMXGPTState *s = IMX_GPT(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
QEMUBH *bh;
sysbus_init_irq(sbd, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
0x00001000);
sysbus_init_mmio(sbd, &s->iomem);
bh = qemu_bh_new(imx_gpt_timeout, s);
s->timer = ptimer_init(bh);
}
static int lm32_timer_init(SysBusDevice *dev)
{
LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
sysbus_init_irq(dev, &s->irq);
s->bh = qemu_bh_new(timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->freq_hz);
memory_region_init_io(&s->iomem, &timer_ops, s, "timer", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static void digic_timer_init(Object *obj)
{
DigicTimerState *s = DIGIC_TIMER(obj);
s->ptimer = ptimer_init(NULL, PTIMER_POLICY_DEFAULT);
/*
* FIXME: there is no documentation on Digic timer
* frequency setup so let it always run at 1 MHz
*/
ptimer_set_freq(s->ptimer, 1 * 1000 * 1000);
memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s,
TYPE_DIGIC_TIMER, 0x100);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
}
static void xlx_iom_realize(DeviceState *dev, Error **errp)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(dev);
unsigned int i;
s->prefix = object_get_canonical_path(OBJECT(dev));
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
RegisterInfo *r = &s->regs_info[i];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[i],
.data_size = sizeof(uint32_t),
.access = &pit_regs_info[i],
.debug = XILINX_IO_MODULE_PIT_ERR_DEBUG,
.prefix = s->prefix,
.opaque = s,
};
memory_region_init_io(&r->mem, OBJECT(dev), &iom_pit_ops, r,
r->access->name, 4);
memory_region_add_subregion(&s->iomem, i * 4, &r->mem);
}
if (s->cfg.use) {
s->bh = qemu_bh_new(pit_timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->frequency);
/* IRQ out to pulse when present timer expires/reloads */
qdev_init_gpio_out(dev, &s->hit_out, 1);
/* IRQ in to enable pre-scalar mode. Routed from gpo1 */
qdev_init_gpio_in_named(dev, iom_pit_ps_config, "ps_config", 1);
/* hit_out of neighbouring PIT is received as hit_in */
qdev_init_gpio_in_named(dev, iom_pit_ps_hit_in, "ps_hit_in", 1);
}
}
static void xlx_iom_pit_init(Object *obj)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &iom_pit_ops, s,
TYPE_XILINX_IO_MODULE_PIT,
R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static int lm32_timer_init(SysBusDevice *dev)
{
LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
int timer_regs;
sysbus_init_irq(dev, &s->irq);
s->bh = qemu_bh_new(timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->freq_hz);
timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, timer_regs);
return 0;
}
void
test_dmatrix_power_uint(int n, uint p, int print)
{
double **out, **in;
pTimer t; ptimer_init(&t, CLOCK_PROCESS_CPUTIME_ID);
in = doubleAA_malloc(n, n);
dmatrix_ramp(in, n, n, 0.0, 2 * n, 1.0);
if (print) {
dmatrix_print((const double **) in, n, n);
puts("");
}
out = doubleAA_malloc(n, n);
ptimer_tic(&t);
dmatrix_mmul(out,
(const double **) in, (const double **) in,
n, n, n);
ptimer_toc(&t);
printf("dmatrix_mmul: ");
siunit_show(ptimer_get_sec(&t));
puts("\n");
if (print) {
dmatrix_print((const double **) out, n, n);
puts("");
}
ptimer_tic(&t);
dmatrix_mmul_strassen(out,
(const double **) in, (const double **) in, n, n,
n);
ptimer_toc(&t);
printf("dmatrix_mmul_strassen: ");
siunit_show(ptimer_get_sec(&t));
puts("\n");
if (print) {
dmatrix_print((const double **) out, n, n);
}
dmatrix_free(in);
dmatrix_free(out);
}
void
test_kdTree_rbal(kdTree * tree, int show)
{
pTimer tmr; ptimer_init(&tmr, CLOCK_PROCESS_CPUTIME_ID);
ptimer_tic(&tmr);
kdTree_rbal(tree);
ptimer_toc(&tmr);
printf("- Balance: "); ptimer_print_sec_usec9(tmr); printf("[s]");
if (show_bars) {
int x = (int)rint(ptimer_get_sec(&tmr) * fac);
mputchar(stdout, x, '#');
}
endline();
}
static void mss_timer_init(Object *obj)
{
MSSTimerState *t = MSS_TIMER(obj);
int i;
/* Init all the ptimers. */
for (i = 0; i < NUM_TIMERS; i++) {
struct Msf2Timer *st = &t->timers[i];
st->bh = qemu_bh_new(timer_hit, st);
st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
ptimer_set_freq(st->ptimer, t->freq_hz);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
}
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
NUM_TIMERS * R_TIM1_MAX * 4);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
}
void
test_kdTree_ins_shape(kdTree * tree,
vis_t ** grid, size_t m, size_t n, int show)
{
size_t k;
pTimer tmr; ptimer_init(&tmr, CLOCK_PROCESS_CPUTIME_ID);
ptimer_tic(&tmr);
for (k = 0; k < m * n; k++) {
vis_t * elm = grid[k];
if (show) {
printf("inserting ");
vis_fprint(stdout, elm);
printf(" nr:%zd/%zd...", k, m * n);
}
kdTree_ins_shape(tree, elm);
if (show) {
kdTree_fprint(stdout, tree, TRUE);
putsep(stdout);
}
if (show) {
endline();
}
}
ptimer_toc(&tmr);
printf("- Insertion: "); ptimer_print_sec_usec9(tmr); printf("[s]");
if (show_bars) {
int x = (int)rint(ptimer_get_sec(&tmr) * fac);
putchar(' ');
mputchar(stdout, x, '#');
}
endline();
}
void
test_kdTree_find_shape(kdTree * tree,
vis_t ** grid, size_t m, size_t n, int show)
{
size_t k;
pTimer tmr; ptimer_init(&tmr, CLOCK_PROCESS_CPUTIME_ID);
ptimer_tic(&tmr);
kdTree_reset_fbs(tree);
size_t hitnum = 0;
for (k = 0; k < m * n; k++) {
const vis_t * elm = grid[k];
if (show) {
printf("finding ");
vis_fprint(stdout, elm);
printf(" nr:%zd/%zd...", k, m * n);
}
int hit = kdTree_find_shape(tree, elm);
if (hit) { hitnum++; }
if (show) {
printf("%s", hit ? "HIT: " : "MISS");
endline();
}
}
ptimer_toc(&tmr);
printf("- Find: "); ptimer_print_sec_usec9(tmr); printf("[s]");
printf(" (%zd) %s ", hitnum, (hitnum == m * n) ? "SUCCESS" : "FAILURE");
if (show_bars) {
int x = (int)rint(ptimer_get_sec(&tmr) * fac);
mputchar(stdout, x, '#');
}
endline();
}
void
test_kdTree_rm_shape(kdTree * tree,
vis_t ** grid, size_t m, size_t n, int show)
{
pTimer tmr; ptimer_init(&tmr, CLOCK_PROCESS_CPUTIME_ID);
ptimer_tic(&tmr);
size_t k, rmnum = 0;
for (k = 0; k < m * n; k++) {
vis_t * elm = grid[k];
if (show) {
printf("removing ");
vis_fprint(stdout, elm);
printf(" nr:%zd/%zd...", k, m * n);
}
uint ok = kdTree_rm_shape(tree, elm);
if (ok) {
rmnum++;
}
if (show) {
printf("%s\n", ok ? "HIT" : "MISS");
}
}
ptimer_toc(&tmr);
printf("- Remove: "); ptimer_print_sec_usec9(tmr); printf("[s]");
printf(" (%zd) %s ", rmnum, (rmnum == m * n) ? "SUCCESS" : "FAILURE");
if (show_bars) {
int x = (int)rint(ptimer_get_sec(&tmr) * fac);
mputchar(stdout, x, '#');
}
endline();
}
static void xilinx_timer_realize(DeviceState *dev, Error **errp)
{
struct timerblock *t = XILINX_TIMER(dev);
unsigned int i;
/* Init all the ptimers. */
t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
for (i = 0; i < num_timers(t); i++) {
struct xlx_timer *xt = &t->timers[i];
xt->parent = t;
xt->nr = i;
xt->bh = qemu_bh_new(timer_hit, xt);
xt->ptimer = ptimer_init(xt->bh);
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
R_MAX * 4 * num_timers(t));
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
}
static int puv3_ost_init(SysBusDevice *dev)
{
PUV3OSTState *s = FROM_SYSBUS(PUV3OSTState, dev);
s->reg_OIER = 0;
s->reg_OSSR = 0;
s->reg_OSMR0 = 0;
s->reg_OSCR = 0;
sysbus_init_irq(dev, &s->irq);
s->bh = qemu_bh_new(puv3_ost_tick, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
memory_region_init_io(&s->iomem, &puv3_ost_ops, s, "puv3_ost",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static int rtt_init(SysBusDevice *dev)
{
rtt_state *s = FROM_SYSBUS(rtt_state, dev);
QEMUBH *bh;
memory_region_init_io(&s->iomem, OBJECT(s), &rtt_ops, s, "rtt", 0x20);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
//s->ssi = ssi_create_bus(&dev->qdev, "ssi");
//rtt_reset(s);
//vmstate_register(&dev->qdev, -1, &vmstate_rtt, s);
bh = qemu_bh_new(rtt_tick, s);
s->timer = ptimer_init(bh);
ptimer_set_freq(s->timer, 10);
ptimer_set_limit(s->timer, 1, 1);
ptimer_run(s->timer, 0);
return 0;
}
static int puv3_ost_init(SysBusDevice *dev)
{
PUV3OSTState *s = PUV3_OST(dev);
s->reg_OIER = 0;
s->reg_OSSR = 0;
s->reg_OSMR0 = 0;
s->reg_OSCR = 0;
sysbus_init_irq(dev, &s->irq);
s->bh = qemu_bh_new(puv3_ost_tick, s);
s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
void pal_startTimers(void) {
// Initialize the hardware to drive the
// signal processing layers.
ctimer_set_callback(pal_captureTimerFn);
comparator_enablePin(LEFT_PORT, LEFT_PIN);
comparator_enablePin(VREF_PORT, VREF_PIN);
comparator_init();
comparator_setup(
comparator_getChannel(LEFT_PORT, LEFT_PIN),
comparator_getChannel(VREF_PORT, VREF_PIN)
);
comparator_on();
ctimer_init();
ptimer_init();
ptimer_start(TIMER_TICKS, pal_periodicTimerFn);
// Wait 100ms for everything to stabalize.
//util_delayMs(100);
}
void
test_no_branching(void)
{
int n;
for (n = 16; n < 1024*1024*64; n *= 2) {
int i;
int std_sum, nob_sum;
pTimer tmr; ptimer_init(&tmr, CLOCK_PROCESS_CPUTIME_ID);
printf("n:%d ", n);
ptimer_tic(&tmr);
std_sum = 0;
for (i = 0; i < n; i++) {
std_sum ^= int_min2(i, n - i);
}
ptimer_toc(&tmr);
printf("std:"); ptimer_print_sec_usec9(tmr);
ptimer_tic(&tmr);
nob_sum = 0;
for (i = 0; i < n; i++) {
nob_sum ^= int_min_no_branching(i, n - i);
}
ptimer_toc(&tmr);
printf(" nob:"); ptimer_print_sec_usec9(tmr);
if (std_sum != nob_sum) {
printf(" NOT EQUAL!");
} else {
printf(" sum:%d", std_sum);
}
endline();
}
}
static int grlib_gptimer_init(SysBusDevice *dev)
{
GPTimerUnit *unit = FROM_SYSBUS(typeof(*unit), dev);
unsigned int i;
int timer_regs;
assert(unit->nr_timers > 0);
assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
unit->timers = qemu_mallocz(sizeof unit->timers[0] * unit->nr_timers);
for (i = 0; i < unit->nr_timers; i++) {
GPTimer *timer = &unit->timers[i];
timer->unit = unit;
timer->bh = qemu_bh_new(grlib_gptimer_hit, timer);
timer->ptimer = ptimer_init(timer->bh);
timer->id = i;
/* One IRQ line for each timer */
sysbus_init_irq(dev, &timer->irq);
ptimer_set_freq(timer->ptimer, unit->freq_hz);
}
timer_regs = cpu_register_io_memory(grlib_gptimer_read,
grlib_gptimer_write,
unit, DEVICE_NATIVE_ENDIAN);
if (timer_regs < 0) {
return -1;
}
sysbus_init_mmio(dev, UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers,
timer_regs);
return 0;
}
