s32_t pwrctrl_sleep_tele_vote_wake_status(u32_t teleModeId)
{
ST_VOTE_HW_INFO * pStVoteInfo = NULL ;
pStVoteInfo = (ST_VOTE_HW_INFO *)g_aAcpuHwVoteBaseAddr[teleModeId];
return pwrctrl_read_reg32(&(pStVoteInfo->voteWakeStat));
}
u32_t pwrctrl_get_timer_cnt( u32_t timerId)
{
u32_t load_val = 0;
u32_t curr_val = 0;
u32_t ulTimerAddr = 0;
ulTimerAddr = pwrctrl_get_timer_base_addr(timerId);
curr_val = pwrctrl_read_reg32(PWRCTRL_TIMER_VALUE_ADDR(ulTimerAddr));
/*
* Here we need do one more step to check if current timer count is valid.
* If curr_val>load_val, we think curr_val is invalid and return the
* load_val. It is a SOC bug, but we just evade it.
*/
load_val = pwrctrl_read_reg32(PWRCTRL_TIMER_LOAD_ADDR(ulTimerAddr));
return curr_val>load_val ? load_val : curr_val;
}
u32_t pwrctrl_get_timer_active( u32_t timerId)
{
u32_t ulControlVal;
u32_t ulTimerValue;
u32_t ulTimerAddr = 0;
ulTimerAddr = pwrctrl_get_timer_base_addr(timerId);
ulControlVal = pwrctrl_read_reg32(PWRCTRL_TIMER_CONTROL_ADDR(ulTimerAddr));
ulTimerValue = pwrctrl_read_reg32(PWRCTRL_TIMER_VALUE_ADDR(ulTimerAddr));
if((0 == (ulControlVal & PWRCTRL_ENABLE)) || (0 == (ulControlVal & PWRCTRL_INTENABLE))
|| ((0 == (ulControlVal & PWRCTRL_FREE)) && (0 == ulTimerValue)) )
{
return PWRCTRL_FALSE;
}
return PWRCTRL_TRUE;
}
void pwrctrl_write_reg32_mask (u32_t ulRegAddr, u32_t ulRegVal, u32_t ulMask)
{
u32_t reg_val = pwrctrl_read_reg32(ulRegAddr);
pwrctrl_clr_bits((u32_t)®_val, ulMask);
pwrctrl_set_bits((u32_t)®_val, ulRegVal & ulMask);
pwrctrl_write_reg32(ulRegAddr, reg_val);
}
u32_t pwrctrl_is_bit_set ( u32_t addr, u32_t offset)
{
if ((pwrctrl_read_reg32(addr) & (1<<offset)) == (1<<offset))
{
return PWRCTRL_TRUE ;
}
else
{
return PWRCTRL_FALSE;
}
}
s32_t pwrctrl_clr_bits (u32_t ulRegAddr, u32_t ulMask)
{
if (0 != (ulRegAddr & 0x03))/* not 4byte aligned */
{
PWC_TRACE(PWC_LOG_MAX, "pwrctrl_clr_bits Address: 0x%x not aligned.\r\n", (int)ulRegAddr,0,0,0,0,0);
return RET_ERR;
}
pwrctrl_write_reg32(ulRegAddr, pwrctrl_read_reg32(ulRegAddr)&(~ulMask));
return RET_OK;
}
s32_t pwrctrl_mem_cpy ( void_t * dest, void_t * src, u32_t size )
{
u32_t length = 0;
u32_t * tDest = (u32_t *)(dest);
u32_t * tSrc = (u32_t *)(src);
for(; length<size; length++)
{
pwrctrl_write_reg32((u32_t)tDest,pwrctrl_read_reg32((u32_t)tSrc));
tDest ++;
tSrc ++;
}
return RET_OK;
}
s32_t __init pwrctrl_common_initial ( void_t )
{
/*lint -e553*/
#if 1/*(FEATURE_POWER_DRV == FEATURE_ON)*/
/*lint +e553*/
local_t u32_t startTm=0;
u32_t tmpTm = 0;
g_stAcpuPwcExcLog = (PWRCTRL_ACPU_EXC_LOG_STRU *)(EXCH_ACPU_CORE_PWC_ADDR_V);
pwrctrl_write_reg32(IO_ADDRESS(EXCH_A_CORE_POWRCTRL_CONV_ADDR), EXCH_ACPU_CORE_PWC_ADDR);
#if 0
g_stMcuLogExt = (PWC_MCU_EXC_LOG_STRU *)ioremap(pwrctrl_read_reg32(MEMORY_AXI_MCU_LOG_ADDR), 0x1000);
#endif
/*保存SLICE TIMER 基地址*/
#if defined(CHIP_BB_HI6210) /*B020 Modify*/
#else
pwrctrl_write_reg32(PWRCTRL_ACPU_ASM_SLICE_BAK_ADDR, IO_ADDRESS(SOC_AO_SCTRL_SC_SLICER_COUNT0_ADDR(SOC_SC_ON_BASE_ADDR)));
#endif
wake_lock_init(&g_ulTstwakelock,WAKE_LOCK_SUSPEND,"pwrctrl_tst");
pwrctrl_sleep_initial();
pwrctrl_sleep_mgr_sleep_init();
if(RET_OK != pwrctrl_is_func_on(PWC_SWITCH_ASLEEP))
{
wake_lock(&g_ulTstwakelock);
PWC_TRACE(PWC_LOG_MAX, "MCU: pwc_common_initial,msleep not support!\r\n",0,0,0,0,0,0);
}
else
{
/*lint*/
}
/* 低功耗初始化完成*/
PWC_TRACE(PWC_LOG_MAX, "ACPU: Enter pwrctrl initial routing! \n",0,0,0,0,0,0);
register_reboot_notifier(&pm_reboot_nb);
pwrctrl_write_reg32(IO_ADDRESS(MEMORY_AXI_SEC_CORE_BOOT_TEST_ADDR), 0);
printk("sec core boot test addr:0x%x\n", MEMORY_AXI_SEC_CORE_BOOT_TEST_ADDR);
#endif
g_pwc_init_flag = PWRCTRL_INIT_FLAG;
return RET_OK;
}
/*****************************************************************************
函 数 名 : pwrctrl_get_timer_count
功能描述 : 获取TIMER的当前计数值(sliceTimer)
输入参数 : 无
输出参数 : 无
返 回 值 : 定时器计数值；
调用函数 :
被调函数 :
修改历史 :
1.日 期 : 2012年8月7日
作 者 : 刘永富 56193
修改内容 : 新生成函数
*****************************************************************************/
u32_t pwrctrl_get_timer_count( void_t )
{
return pwrctrl_read_reg32(PWRCTRL_SLICE_TIMER_VADDR);
}
bool_t pwrctrl_is_bits_clr(u32_t ulRegAddr, u32_t ulMask)
{
LOG_IF (0 != (ulRegAddr & 0x03));
return (pwrctrl_read_reg32(ulRegAddr) & ulMask) == 0x0;
}
u32_t pwrctrl_read_reg32_mask(u32_t ulRegAddr, u32_t ulMask)
{
return pwrctrl_read_reg32(ulRegAddr) & ulMask;
}
