static void arm_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); static bool inited; cs->env_ptr = &cpu->env; cpu_exec_init(&cpu->env); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); } else { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); } cpu->gt_timer[GTIMER_PHYS] = qemu_new_timer(vm_clock, GTIMER_SCALE, arm_gt_ptimer_cb, cpu); cpu->gt_timer[GTIMER_VIRT] = qemu_new_timer(vm_clock, GTIMER_SCALE, arm_gt_vtimer_cb, cpu); qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, ARRAY_SIZE(cpu->gt_timer_outputs)); #endif if (tcg_enabled() && !inited) { inited = true; arm_translate_init(); } }
static int realview_gic_init(SysBusDevice *dev) { RealViewGICState *s = FROM_SYSBUS(RealViewGICState, dev); SysBusDevice *busdev; /* The GICs on the RealView boards have a fixed nonconfigurable * number of interrupt lines, so we don't need to expose this as * a qdev property. */ int numirq = 96; s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", 1); qdev_prop_set_uint32(s->gic, "num-irq", numirq); qdev_init_nofail(s->gic); busdev = sysbus_from_qdev(s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(&s->busdev.qdev, realview_gic_set_irq, numirq - 32); memory_region_init(&s->container, "realview-gic-container", 0x2000); memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(busdev, 1)); memory_region_add_subregion(&s->container, 0x1000, sysbus_mmio_get_region(busdev, 0)); sysbus_init_mmio(dev, &s->container); return 0; }
static void altera_iic_init(Object *obj) { AlteraIIC *pv = ALTERA_IIC(obj); qdev_init_gpio_in(DEVICE(pv), irq_handler, 32); sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq); }
static void kvm_openpic_realize(DeviceState *dev, Error **errp) { SysBusDevice *d = SYS_BUS_DEVICE(dev); KVMOpenPICState *opp = KVM_OPENPIC(dev); KVMState *s = kvm_state; int kvm_openpic_model; struct kvm_create_device cd = {0}; int ret, i; if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) { error_setg(errp, "Kernel is lacking Device Control API"); return; } switch (opp->model) { case OPENPIC_MODEL_FSL_MPIC_20: kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20; break; case OPENPIC_MODEL_FSL_MPIC_42: kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42; break; default: error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model); return; } cd.type = kvm_openpic_model; ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd); if (ret < 0) { error_setg(errp, "Can't create device %d: %s", cd.type, strerror(errno)); return; } opp->fd = cd.fd; sysbus_init_mmio(d, &opp->mem); qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ); opp->mem_listener.region_add = kvm_openpic_region_add; opp->mem_listener.region_del = kvm_openpic_region_del; memory_listener_register(&opp->mem_listener, &address_space_memory); /* indicate pic capabilities */ msi_nonbroken = true; kvm_kernel_irqchip = true; kvm_async_interrupts_allowed = true; /* set up irq routing */ kvm_init_irq_routing(kvm_state); for (i = 0; i < 256; ++i) { kvm_irqchip_add_irq_route(kvm_state, i, 0, i); } kvm_msi_via_irqfd_allowed = true; kvm_gsi_routing_allowed = true; kvm_irqchip_commit_routes(s); }
static int mpcore_priv_init(SysBusDevice *dev) { ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev); s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); /* Request the legacy 11MPCore GIC behaviour: */ qdev_prop_set_uint32(s->gic, "revision", 0); qdev_init_nofail(s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic)); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32); s->mptimer = qdev_create(NULL, "arm_mptimer"); qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); qdev_init_nofail(s->mptimer); s->wdtimer = qdev_create(NULL, "arm_mptimer"); qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); qdev_init_nofail(s->wdtimer); mpcore_priv_map_setup(s); sysbus_init_mmio(dev, &s->container); return 0; }
static void altera_iic_init(Object *obj) { AlteraIIC *pv = ALTERA_IIC(obj); qdev_init_gpio_in(DEVICE(pv), irq_handler, 32); qdev_init_gpio_out_named(DEVICE(obj), &pv->parent_irq, "irq", 1); }
static int realview_mpcore_init(SysBusDevice *dev) { mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); DeviceState *gic; DeviceState *priv; int n; int i; priv = qdev_create(NULL, "arm11mpcore_priv"); qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); qdev_init_nofail(priv); s->priv = SYS_BUS_DEVICE(priv); sysbus_pass_irq(dev, s->priv); for (i = 0; i < 32; i++) { s->cpuic[i] = qdev_get_gpio_in(priv, i); } /* ??? IRQ routing is hardcoded to "normal" mode. */ for (n = 0; n < 4; n++) { gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, s->cpuic[10 + n]); for (i = 0; i < 64; i++) { s->rvic[n][i] = qdev_get_gpio_in(gic, i); } } qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0)); return 0; }
static int goldfish_int_init(GoldfishDevice *dev) { GoldfishInterruptDevice *idev = (GoldfishInterruptDevice *)dev; qdev_init_gpio_in(&idev->dev.qdev, goldfish_int_set_irq, 32); return 0; }
static void or_irq_realize(DeviceState *dev, Error **errp) { qemu_or_irq *s = OR_IRQ(dev); assert(s->num_lines < MAX_OR_LINES); qdev_init_gpio_in(dev, or_irq_handler, s->num_lines); }
static int a15mp_priv_init(SysBusDevice *dev) { A15MPPrivState *s = A15MPCORE_PRIV(dev); SysBusDevice *busdev; const char *gictype = "arm_gic"; int i; if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; } s->gic = qdev_create(NULL, gictype); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); qdev_prop_set_uint32(s->gic, "revision", 2); qdev_init_nofail(s->gic); busdev = SYS_BUS_DEVICE(s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32); /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs */ for (i = 0; i < s->num_cpu; i++) { DeviceState *cpudev = DEVICE(qemu_get_cpu(i)); int ppibase = s->num_irq - 32 + i * 32; /* physical timer; we wire it up to the non-secure timer's ID, * since a real A15 always has TrustZone but QEMU doesn't. */ qdev_connect_gpio_out(cpudev, 0, qdev_get_gpio_in(s->gic, ppibase + 30)); /* virtual timer */ qdev_connect_gpio_out(cpudev, 1, qdev_get_gpio_in(s->gic, ppibase + 27)); } /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved * 0x1000-0x1fff -- GIC Distributor * 0x2000-0x2fff -- GIC CPU interface * 0x4000-0x4fff -- GIC virtual interface control (not modelled) * 0x5000-0x5fff -- GIC virtual interface control (not modelled) * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) */ memory_region_init(&s->container, OBJECT(s), "a15mp-priv-container", 0x8000); memory_region_add_subregion(&s->container, 0x1000, sysbus_mmio_get_region(busdev, 0)); memory_region_add_subregion(&s->container, 0x2000, sysbus_mmio_get_region(busdev, 1)); sysbus_init_mmio(dev, &s->container); return 0; }
static void lm32_pic_init(Object *obj) { DeviceState *dev = DEVICE(obj); LM32PicState *s = LM32_PIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); qdev_init_gpio_in(dev, irq_handler, 32); sysbus_init_irq(sbd, &s->parent_irq); }
static int altera_iic_init(SysBusDevice *dev) { AlteraIIC *pv = ALTERA_IIC(dev); qdev_init_gpio_in(DEVICE(pv), irq_handler, 32); sysbus_init_irq(dev, &pv->parent_irq); return 0; }
static int arm_sysctl_init(SysBusDevice *dev) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000); sysbus_init_mmio(dev, &s->iomem); qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2); qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1); return 0; }
static void bcm2835_mbox_init(Object *obj) { BCM2835MboxState *s = BCM2835_MBOX(obj); memory_region_init_io(&s->iomem, obj, &bcm2835_mbox_ops, s, TYPE_BCM2835_MBOX, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); sysbus_init_irq(SYS_BUS_DEVICE(s), &s->arm_irq); qdev_init_gpio_in(DEVICE(s), bcm2835_mbox_set_irq, MBOX_CHAN_COUNT); }
static int exynos4210_gic_init(SysBusDevice *dev) { Exynos4210GicState *s = FROM_SYSBUS(Exynos4210GicState, dev); uint32_t i; const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; const char dist_prefix[] = "exynos4210-gic-alias_dist"; char cpu_alias_name[sizeof(cpu_prefix) + 3]; char dist_alias_name[sizeof(cpu_prefix) + 3]; SysBusDevice *busdev; s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", EXYNOS4210_GIC_NIRQ); qdev_init_nofail(s->gic); busdev = SYS_BUS_DEVICE(s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev); /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(&s->busdev.qdev, exynos4210_gic_set_irq, EXYNOS4210_GIC_NIRQ - 32); memory_region_init(&s->cpu_container, "exynos4210-cpu-container", EXYNOS4210_EXT_GIC_CPU_REGION_SIZE); memory_region_init(&s->dist_container, "exynos4210-dist-container", EXYNOS4210_EXT_GIC_DIST_REGION_SIZE); for (i = 0; i < s->num_cpu; i++) { /* Map CPU interface per SMP Core */ sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); memory_region_init_alias(&s->cpu_alias[i], cpu_alias_name, sysbus_mmio_get_region(busdev, 1), 0, EXYNOS4210_GIC_CPU_REGION_SIZE); memory_region_add_subregion(&s->cpu_container, EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]); /* Map Distributor per SMP Core */ sprintf(dist_alias_name, "%s%x", dist_prefix, i); memory_region_init_alias(&s->dist_alias[i], dist_alias_name, sysbus_mmio_get_region(busdev, 0), 0, EXYNOS4210_GIC_DIST_REGION_SIZE); memory_region_add_subregion(&s->dist_container, EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]); } sysbus_init_mmio(dev, &s->cpu_container); sysbus_init_mmio(dev, &s->dist_container); return 0; }
static int icp_pic_init(SysBusDevice *dev) { icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev); qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32); sysbus_init_irq(dev, &s->parent_irq); sysbus_init_irq(dev, &s->parent_fiq); memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000); sysbus_init_mmio(dev, &s->iomem); return 0; }
static int xilinx_intc_init(SysBusDevice *dev) { struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev); qdev_init_gpio_in(&dev->qdev, irq_handler, 32); sysbus_init_irq(dev, &p->parent_irq); memory_region_init_io(&p->mmio, &pic_ops, p, "xilinx-pic", R_MAX * 4); sysbus_init_mmio(dev, &p->mmio); return 0; }
static int lm32_pic_init(SysBusDevice *dev) { LM32PicState *s = FROM_SYSBUS(typeof(*s), dev); qdev_init_gpio_in(&dev->qdev, irq_handler, 32); sysbus_init_irq(dev, &s->parent_irq); pic = s; return 0; }
static void xilinx_intc_init(SysBusDevice *dev) { struct xlx_pic *p = FROM_SYSBUS(typeof (*p), dev); int pic_regs; qdev_init_gpio_in(&dev->qdev, irq_handler, 32); sysbus_init_irq(dev, &p->parent_irq); pic_regs = cpu_register_io_memory(pic_read, pic_write, p); sysbus_init_mmio(dev, R_MAX * 4, pic_regs); }
static void arm_sysctl_init(Object *obj) { DeviceState *dev = DEVICE(obj); SysBusDevice *sd = SYS_BUS_DEVICE(obj); arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sd); memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000); sysbus_init_mmio(sd, &s->iomem); qdev_init_gpio_in(dev, arm_sysctl_gpio_set, 2); qdev_init_gpio_out(dev, &s->pl110_mux_ctrl, 1); }
static void xlnx_axi_gpio_realize(DeviceState *dev, Error **errp) { XlnxAXIGPIO *s = XLNX_AXI_GPIO(dev); const char *prefix = object_get_canonical_path(OBJECT(dev)); unsigned int i; for (i = 0; i < ARRAY_SIZE(xlnx_axi_gpio_regs_info); ++i) { DepRegisterInfo *r = &s->regs_info[xlnx_axi_gpio_regs_info[i].decode.addr/4]; *r = (DepRegisterInfo) { .data = (uint8_t *)&s->regs[ xlnx_axi_gpio_regs_info[i].decode.addr/4], .data_size = sizeof(uint32_t), .access = &xlnx_axi_gpio_regs_info[i], .debug = XLNX_AXI_GPIO_ERR_DEBUG, .prefix = prefix, .opaque = s, }; } /* Create two GPIO in banks that QTest can use */ qdev_init_gpio_in(dev, data_handler1, 32); qdev_init_gpio_in(dev, data_handler2, 32); /* Create GPIO banks as well */ qdev_init_gpio_out(dev, s->outputs1, 32); qdev_init_gpio_out(dev, s->outputs2, 32); } static void xlnx_axi_gpio_init(Object *obj) { XlnxAXIGPIO *s = XLNX_AXI_GPIO(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); memory_region_init_io(&s->iomem, obj, &xlnx_axi_gpio_ops, s, TYPE_XLNX_AXI_GPIO, R_MAX * 4); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->parent_irq); }
static int strongarm_pic_initfn(SysBusDevice *dev) { StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev); qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS); memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000); sysbus_init_mmio(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); sysbus_init_irq(dev, &s->fiq); return 0; }
static void aw_a10_pic_init(Object *obj) { AwA10PICState *s = AW_A10_PIC(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); qdev_init_gpio_in(DEVICE(dev), aw_a10_pic_set_irq, AW_A10_PIC_INT_NR); sysbus_init_irq(dev, &s->parent_irq); sysbus_init_irq(dev, &s->parent_fiq); memory_region_init_io(&s->iomem, OBJECT(s), &aw_a10_pic_ops, s, TYPE_AW_A10_PIC, 0x400); sysbus_init_mmio(dev, &s->iomem); }
static void arm_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); static bool inited; cs->env_ptr = &cpu->env; cpu_exec_init(&cpu->env); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); } else { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); } cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, arm_gt_ptimer_cb, cpu); cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, arm_gt_vtimer_cb, cpu); qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, ARRAY_SIZE(cpu->gt_timer_outputs)); #endif /* DTB consumers generally don't in fact care what the 'compatible' * string is, so always provide some string and trust that a hypothetical * picky DTB consumer will also provide a helpful error message. */ cpu->dtb_compatible = "qemu,unknown"; cpu->psci_version = 1; /* By default assume PSCI v0.1 */ cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; if (tcg_enabled() && !inited) { inited = true; arm_translate_init(); } }
static void strongarm_pic_initfn(Object *obj) { DeviceState *dev = DEVICE(obj); StrongARMPICState *s = STRONGARM_PIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS); memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s, "pic", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); sysbus_init_irq(sbd, &s->fiq); }
static int arm_sysctl_init1(SysBusDevice *dev) { arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); int iomemtype; iomemtype = cpu_register_io_memory(arm_sysctl_readfn, arm_sysctl_writefn, s, DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, iomemtype); qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2); /* ??? Save/restore. */ return 0; }
static void sparc32_dma_init(Object *obj) { DeviceState *dev = DEVICE(obj); DMAState *s = SPARC32_DMA(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); sysbus_init_irq(sbd, &s->irq); sysbus_init_mmio(sbd, &s->iomem); qdev_init_gpio_in(dev, dma_set_irq, 1); qdev_init_gpio_out(dev, s->gpio, 2); }
static int xilinx_intc_init(SysBusDevice *sbd) { DeviceState *dev = DEVICE(sbd); struct xlx_pic *p = XILINX_INTC(dev); qdev_init_gpio_in(dev, irq_handler, 32); sysbus_init_irq(sbd, &p->parent_irq); memory_region_init_io(&p->mmio, OBJECT(p), &pic_ops, p, "xlnx.xps-intc", R_MAX * 4); sysbus_init_mmio(sbd, &p->mmio); return 0; }
static void imx_gpio_realize(DeviceState *dev, Error **errp) { IMXGPIOState *s = IMX_GPIO(dev); memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s, TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE); qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT); qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT); sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); }
static int tusb6010_init(SysBusDevice *dev) { TUSBState *s = FROM_SYSBUS(TUSBState, dev); s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s); s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s); memory_region_init_io(&s->iomem[1], &tusb_async_ops, s, "tusb-async", UINT32_MAX); sysbus_init_mmio(dev, &s->iomem[0]); sysbus_init_mmio(dev, &s->iomem[1]); sysbus_init_irq(dev, &s->irq); qdev_init_gpio_in(&dev->qdev, tusb6010_irq, musb_irq_max + 1); s->musb = musb_init(&dev->qdev, 1); return 0; }