/* Set CPU Timer */
void HELPER(spt)(CPUS390XState *env, uint64_t time)
{
if (time == -1ULL) {
return;
}
/* nanoseconds */
time = (time * 125) >> 9;
timer_mod(env->cpu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
}
static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset,
unsigned size)
{
STM32F2XXTimerState *s = opaque;
DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
switch (offset) {
case TIM_CR1:
return s->tim_cr1;
case TIM_CR2:
return s->tim_cr2;
case TIM_SMCR:
return s->tim_smcr;
case TIM_DIER:
return s->tim_dier;
case TIM_SR:
return s->tim_sr;
case TIM_EGR:
return s->tim_egr;
case TIM_CCMR1:
return s->tim_ccmr1;
case TIM_CCMR2:
return s->tim_ccmr2;
case TIM_CCER:
return s->tim_ccer;
case TIM_CNT:
return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
s->tick_offset;
case TIM_PSC:
return s->tim_psc;
case TIM_ARR:
return s->tim_arr;
case TIM_CCR1:
return s->tim_ccr1;
case TIM_CCR2:
return s->tim_ccr2;
case TIM_CCR3:
return s->tim_ccr3;
case TIM_CCR4:
return s->tim_ccr4;
case TIM_DCR:
return s->tim_dcr;
case TIM_DMAR:
return s->tim_dmar;
case TIM_OR:
return s->tim_or;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
}
return 0;
}
/* ACPI PM1a EVT */
uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar)
{
/* Compare ns-clock, not PM timer ticks, because
acpi_pm_tmr_update function uses ns for setting the timer. */
int64_t d = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (d >= muldiv64(ar->tmr.overflow_time,
NANOSECONDS_PER_SECOND, PM_TIMER_FREQUENCY)) {
ar->pm1.evt.sts |= ACPI_BITMASK_TIMER_STATUS;
}
return ar->pm1.evt.sts;
}
static void mirror_throttle(MirrorBlockJob *s)
{
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
if (now - s->last_pause_ns > SLICE_TIME) {
s->last_pause_ns = now;
block_job_sleep_ns(&s->common, 0);
} else {
block_job_pause_point(&s->common);
}
}
static void continue_send(IPMIBmcExtern *ibe)
{
if (ibe->outlen == 0) {
goto check_reset;
}
send:
ibe->outpos += qemu_chr_fe_write(ibe->chr, ibe->outbuf + ibe->outpos,
ibe->outlen - ibe->outpos);
if (ibe->outpos < ibe->outlen) {
/* Not fully transmitted, try again in a 10ms */
timer_mod_ns(ibe->extern_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 10000000);
} else {
/* Sent */
ibe->outlen = 0;
ibe->outpos = 0;
if (!ibe->sending_cmd) {
ibe->waiting_rsp = true;
} else {
ibe->sending_cmd = false;
}
check_reset:
if (ibe->connected && ibe->send_reset) {
/* Send the reset */
ibe->outbuf[0] = VM_CMD_RESET;
ibe->outbuf[1] = VM_CMD_CHAR;
ibe->outlen = 2;
ibe->outpos = 0;
ibe->send_reset = false;
ibe->sending_cmd = true;
goto send;
}
if (ibe->waiting_rsp) {
/* Make sure we get a response within 4 seconds. */
timer_mod_ns(ibe->extern_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 4000000000ULL);
}
}
return;
}
/* Add elapsed ticks to ttcr */
void cpu_openrisc_count_update(OpenRISCCPU *cpu)
{
uint64_t now;
if (!cpu->env.is_counting) {
return;
}
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
or1k_timer->ttcr += (uint32_t)((now - or1k_timer->last_clk)
/ TIMER_PERIOD);
or1k_timer->last_clk = now;
}
static void rtc_coalesced_timer_update(RTCState *s)
{
if (s->irq_coalesced == 0) {
timer_del(s->coalesced_timer);
} else {
/* divide each RTC interval to 2 - 8 smaller intervals */
int c = MIN(s->irq_coalesced, 7) + 1;
int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
muldiv64(s->period / c, get_ticks_per_sec(), RTC_CLOCK_RATE);
timer_mod(s->coalesced_timer, next_clock);
}
}
void mips_gictimer_stop_count(MIPSGICTimerState *gictimer)
{
int i;
gictimer->countstop = 1;
/* Store the current value */
gictimer->sh_counterlo +=
(uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD);
for (i = 0; i < gictimer->num_vps; i++) {
timer_del(gictimer->vptimers[i].qtimer);
}
}
static void tusb6010_power(TUSBState *s, int on)
{
if (!on) {
s->power = 0;
} else if (!s->power && on) {
s->power = 1;
/* Pull the interrupt down after TUSB6010 comes up. */
s->intr_ok = 0;
tusb_intr_update(s);
timer_mod(s->pwr_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
NANOSECONDS_PER_SECOND / 2);
}
}
/* Set Clock Comparator */
void HELPER(sckc)(CPUS390XState *env, uint64_t time)
{
if (time == -1ULL) {
return;
}
/* difference between now and then */
time -= clock_value(env);
/* nanoseconds */
time = (time * 125) >> 9;
timer_mod(env->tod_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
}
void hid_set_next_idle(HIDState *hs)
{
if (hs->idle) {
uint64_t expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() * hs->idle * 4 / 1000;
if (!hs->idle_timer) {
hs->idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hid_idle_timer, hs);
}
timer_mod_ns(hs->idle_timer, expire_time);
} else {
hid_del_idle_timer(hs);
}
}
static int curl_timer_cb(CURLM *multi, long timeout_ms, void *opaque)
{
BDRVCURLState *s = opaque;
DPRINTF("CURL: timer callback timeout_ms %ld\n", timeout_ms);
if (timeout_ms == -1) {
timer_del(&s->timer);
} else {
int64_t timeout_ns = (int64_t)timeout_ms * 1000 * 1000;
timer_mod(&s->timer,
qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ns);
}
return 0;
}
static void rtc_set_date_from_host(ISADevice *dev)
{
RTCState *s = MC146818_RTC(dev);
struct tm tm;
qemu_get_timedate(&tm, 0);
s->base_rtc = mktimegm(&tm);
s->last_update = qemu_clock_get_ns(rtc_clock);
s->offset = 0;
/* set the CMOS date */
rtc_set_cmos(s, &tm);
}
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
{
uint64_t real_count = count & ~timer->npt_mask;
uint64_t npt_bit = count & timer->npt_mask;
int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
cpu_to_timer_ticks(real_count, timer->frequency);
TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
timer->name, real_count,
timer->npt ? "disabled" : "enabled", timer);
timer->npt = npt_bit ? 1 : 0;
timer->clock_offset = vm_clock_offset;
}
uint64_t cpu_tick_get_count(CPUTimer *timer)
{
uint64_t real_count = timer_to_cpu_ticks(
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
timer->frequency);
TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
timer->name, real_count,
timer->disabled?"disabled":"enabled", timer);
if (timer->disabled)
real_count |= timer->disabled_mask;
return real_count;
}
void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
{
uint64_t real_count = count & ~timer->npt_mask;
uint64_t npt_bit = count & timer->npt_mask;
int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
cpu_to_timer_ticks(real_count, timer->frequency);
trace_sparc64_cpu_tick_set_count(timer->name, real_count,
timer->npt ? "disabled" : "enabled",
timer);
timer->npt = npt_bit ? 1 : 0;
timer->clock_offset = vm_clock_offset;
}
static void dp8393x_set_next_tick(dp8393xState *s)
{
uint32_t ticks;
int64_t delay;
if (s->regs[SONIC_CR] & SONIC_CR_STP) {
timer_del(s->watchdog);
return;
}
ticks = dp8393x_wt(s);
s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
timer_mod(s->watchdog, s->wt_last_update + delay);
}
static void set_next_tick(dp8393xState *s)
{
uint32_t ticks;
int64_t delay;
if (s->regs[SONIC_CR] & SONIC_CR_STP) {
timer_del(s->watchdog);
return;
}
ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
delay = get_ticks_per_sec() * ticks / 5000000;
timer_mod(s->watchdog, s->wt_last_update + delay);
}
/* set irq level. If an edge is detected, then the IRR is set to 1 */
static void pic_set_irq(void *opaque, int irq, int level)
{
PICCommonState *s = opaque;
int mask = 1 << irq;
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \
defined(DEBUG_IRQ_LATENCY)
int irq_index = s->master ? irq : irq + 8;
#endif
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
if (level != irq_level[irq_index]) {
DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index, level);
irq_level[irq_index] = level;
#ifdef DEBUG_IRQ_COUNT
if (level == 1) {
irq_count[irq_index]++;
}
#endif
}
#endif
#ifdef DEBUG_IRQ_LATENCY
if (level) {
irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
#endif
if (s->elcr & mask) {
/* level triggered */
if (level) {
s->irr |= mask;
s->last_irr |= mask;
} else {
s->irr &= ~mask;
s->last_irr &= ~mask;
}
} else {
/* edge triggered */
if (level) {
if ((s->last_irr & mask) == 0) {
s->irr |= mask;
}
s->last_irr |= mask;
} else {
s->last_irr &= ~mask;
}
}
pic_update_irq(s);
}
static void pl031_set_alarm(PL031State *s)
{
uint32_t ticks;
/* The timer wraps around. This subtraction also wraps in the same way,
and gives correct results when alarm < now_ticks. */
ticks = s->mr - pl031_get_count(s);
DPRINTF("Alarm set in %ud ticks\n", ticks);
if (ticks == 0) {
timer_del(s->timer);
pl031_interrupt(s);
} else {
int64_t now = qemu_clock_get_ns(rtc_clock);
timer_mod(s->timer, now + (int64_t)ticks * NANOSECONDS_PER_SECOND);
}
}
/* Used to configure the throttle
*
* @ts: the throttle state we are working on
* @cfg: the config to set
*/
void throttle_config(ThrottleState *ts, ThrottleConfig *cfg)
{
int i;
ts->cfg = *cfg;
for (i = 0; i < BUCKETS_COUNT; i++) {
throttle_fix_bucket(&ts->cfg.buckets[i]);
}
ts->previous_leak = qemu_clock_get_ns(ts->clock_type);
for (i = 0; i < 2; i++) {
throttle_cancel_timer(ts->timers[i]);
}
}
static void pl031_init(Object *obj)
{
PL031State *s = PL031(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
struct tm tm;
memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm) -
qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
}
uint64_t cpu_tick_get_count(CPUTimer *timer)
{
uint64_t real_count = timer_to_cpu_ticks(
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
timer->frequency);
trace_sparc64_cpu_tick_get_count(timer->name, real_count,
timer->npt ? "disabled" : "enabled",
timer);
if (timer->npt) {
real_count |= timer->npt_mask;
}
return real_count;
}
void mips_gictimer_store_sh_count(MIPSGICTimerState *gictimer, uint64_t count)
{
int i;
uint64_t now;
if (gictimer->countstop || !gictimer->vptimers[0].qtimer) {
gictimer->sh_counterlo = count;
} else {
/* Store new count register */
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
gictimer->sh_counterlo = count - (uint32_t)(now / TIMER_PERIOD);
/* Update timer timer */
for (i = 0; i < gictimer->num_vps; i++) {
gic_vptimer_update(gictimer, i, now);
}
}
}
/* handle update-ended timer */
static void check_update_timer(RTCState *s)
{
uint64_t next_update_time;
uint64_t guest_nsec;
int next_alarm_sec;
/* From the data sheet: "Holding the dividers in reset prevents
* interrupts from operating, while setting the SET bit allows"
* them to occur. However, it will prevent an alarm interrupt
* from occurring, because the time of day is not updated.
*/
if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
timer_del(s->update_timer);
return;
}
if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
timer_del(s->update_timer);
return;
}
if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
(s->cmos_data[RTC_REG_C] & REG_C_AF)) {
timer_del(s->update_timer);
return;
}
guest_nsec = get_guest_rtc_ns(s) % NSEC_PER_SEC;
/* if UF is clear, reprogram to next second */
next_update_time = qemu_clock_get_ns(rtc_clock)
+ NSEC_PER_SEC - guest_nsec;
/* Compute time of next alarm. One second is already accounted
* for in next_update_time.
*/
next_alarm_sec = get_next_alarm(s);
s->next_alarm_time = next_update_time + (next_alarm_sec - 1) * NSEC_PER_SEC;
if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
/* UF is set, but AF is clear. Program the timer to target
* the alarm time. */
next_update_time = s->next_alarm_time;
}
if (next_update_time != timer_expire_time_ns(s->update_timer)) {
timer_mod(s->update_timer, next_update_time);
}
}
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
QEMUBHFunc *cb, uint32_t frequency,
uint64_t disabled_mask)
{
CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
timer->name = name;
timer->frequency = frequency;
timer->disabled_mask = disabled_mask;
timer->disabled = 1;
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
return timer;
}
static int
throttlePipe_recvBuffers( void* opaque, GoldfishPipeBuffer* buffers, int numBuffers )
{
ThrottlePipe* pipe = opaque;
int ret;
if (pipe->recvExpiration > 0) {
return PIPE_ERROR_AGAIN;
}
ret = pingPongPipe_recvBuffers(&pipe->pingpong, buffers, numBuffers);
if (ret > 0) {
pipe->recvExpiration = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ret*pipe->recvRate;
throttlePipe_rearm(pipe);
}
return ret;
}
uint32_t mips_gictimer_get_sh_count(MIPSGICTimerState *gictimer)
{
int i;
if (gictimer->countstop) {
return gictimer->sh_counterlo;
} else {
uint64_t now;
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
for (i = 0; i < gictimer->num_vps; i++) {
if (timer_pending(gictimer->vptimers[i].qtimer)
&& timer_expired(gictimer->vptimers[i].qtimer, now)) {
/* The timer has already expired. */
gic_vptimer_expire(gictimer, i, now);
}
}
return gictimer->sh_counterlo + (uint32_t)(now / TIMER_PERIOD);
}
}
static int
throttlePipe_sendBuffers( void* opaque, const GoldfishPipeBuffer* buffers, int numBuffers )
{
ThrottlePipe* pipe = opaque;
int ret;
if (pipe->sendExpiration > 0) {
return PIPE_ERROR_AGAIN;
}
ret = pingPongPipe_sendBuffers(&pipe->pingpong, buffers, numBuffers);
if (ret > 0) {
/* Compute next send expiration time */
pipe->sendExpiration = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ret*pipe->sendRate;
throttlePipe_rearm(pipe);
}
return ret;
}
static void dp8393x_update_wt_regs(dp8393xState *s)
{
int64_t elapsed;
uint32_t val;
if (s->regs[SONIC_CR] & SONIC_CR_STP) {
timer_del(s->watchdog);
return;
}
elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
val = dp8393x_wt(s);
val -= elapsed / 5000000;
s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
dp8393x_set_next_tick(s);
}
