CPUXtensaState *cpu_xtensa_init(const char *cpu_model)
{
static int tcg_inited;
CPUXtensaState *env;
const XtensaConfig *config = NULL;
int i;
for (i = 0; i < ARRAY_SIZE(core_config); ++i)
if (strcmp(core_config[i].name, cpu_model) == 0) {
config = core_config + i;
break;
}
if (config == NULL) {
return NULL;
}
env = g_malloc0(sizeof(*env));
env->config = config;
cpu_exec_init(env);
if (!tcg_inited) {
tcg_inited = 1;
xtensa_translate_init();
}
xtensa_irq_init(env);
qemu_init_vcpu(env);
return env;
}
static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
TriCoreCPU *cpu = TRICORE_CPU(dev);
TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
CPUTriCoreState *env = &cpu->env;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
/* Some features automatically imply others */
if (tricore_feature(env, TRICORE_FEATURE_161)) {
set_feature(env, TRICORE_FEATURE_16);
}
if (tricore_feature(env, TRICORE_FEATURE_16)) {
set_feature(env, TRICORE_FEATURE_131);
}
if (tricore_feature(env, TRICORE_FEATURE_131)) {
set_feature(env, TRICORE_FEATURE_13);
}
cpu_reset(cs);
qemu_init_vcpu(cs);
tcc->parent_realize(dev, errp);
}
LM32CPU *cpu_lm32_init(const char *cpu_model)
{
LM32CPU *cpu;
CPULM32State *env;
const LM32Def *def;
static int tcg_initialized;
def = cpu_lm32_find_by_name(cpu_model);
if (!def) {
return NULL;
}
cpu = LM32_CPU(object_new(TYPE_LM32_CPU));
env = &cpu->env;
env->features = def->features;
env->num_bps = def->num_breakpoints;
env->num_wps = def->num_watchpoints;
env->cfg = cfg_by_def(def);
qemu_init_vcpu(env);
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = 1;
lm32_translate_init();
}
return cpu;
}
Nios2CPU *cpu_nios2_init(const char *cpu_model)
{
Nios2CPU *cpu;
int i;
cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
cpu->env.reset_addr = RESET_ADDRESS;
cpu->env.exception_addr = EXCEPTION_ADDRESS;
cpu->env.fast_tlb_miss_addr = FAST_TLB_MISS_ADDRESS;
cpu_reset(CPU(cpu));
qemu_init_vcpu(&cpu->env);
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
for (i = 0; i < NUM_CORE_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUNios2State, regs[i]),
regnames[i]);
}
#define GEN_HELPER 2
#include "helper.h"
return cpu;
}
static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
{
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
qemu_init_vcpu(CPU(dev));
ucc->parent_realize(dev, errp);
}
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
qemu_init_vcpu(CPU(dev));
scc->parent_realize(dev, errp);
}
static void alpha_cpu_realize(Object *obj, Error **errp)
{
#ifndef CONFIG_USER_ONLY
AlphaCPU *cpu = ALPHA_CPU(obj);
qemu_init_vcpu(&cpu->env);
#endif
}
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
qemu_init_vcpu(cs);
acc->parent_realize(dev, errp);
}
static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
mcc->parent_realize(dev, errp);
}
static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
tcc->parent_realize(dev, errp);
}
static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
tcc->parent_realize(dev, errp);
}
static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
{
SuperHCPU *cpu = SUPERH_CPU(dev);
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
cpu_reset(CPU(cpu));
qemu_init_vcpu(&cpu->env);
scc->parent_realize(dev, errp);
}
static void riscv_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
mcc->parent_realize(dev, errp);
}
static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
qemu_init_vcpu(cs);
cpu_reset(cs);
occ->parent_realize(dev, errp);
}
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
mcc->parent_realize(dev, errp);
}
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
qemu_init_vcpu(cs);
xcc->parent_realize(dev, errp);
}
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
lcc->parent_realize(dev, errp);
}
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
{
LM32CPU *cpu = LM32_CPU(dev);
LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
cpu_reset(CPU(cpu));
qemu_init_vcpu(&cpu->env);
lcc->parent_realize(dev, errp);
}
static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
s390_cpu_gdb_init(cs);
qemu_init_vcpu(cs);
#if !defined(CONFIG_USER_ONLY)
run_on_cpu(cs, s390_do_cpu_full_reset, cs);
#else
cpu_reset(cs);
#endif
scc->parent_realize(dev, errp);
}
static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
qemu_init_vcpu(cs);
acc->parent_realize(dev, errp);
}
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
#if defined(CONFIG_USER_ONLY)
SPARCCPU *cpu = SPARC_CPU(dev);
CPUSPARCState *env = &cpu->env;
if ((env->def->features & CPU_FEATURE_FLOAT)) {
env->def->features |= CPU_FEATURE_FLOAT128;
}
#endif
qemu_init_vcpu(CPU(dev));
scc->parent_realize(dev, errp);
}
CPUAVR32State *cpu_avr32_init(const char *cpu_model)
{
/* SN: TBD */
CPUAVR32State *env;
static int inited = 0;
env = g_malloc0(sizeof(CPUAVR32State));
cpu_exec_init(env);
if (!inited) {
inited = 1;
avr32_translate_init();
}
cpu_reset(env);
qemu_init_vcpu(env);
return env;
}
static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
cpu_reset(cs);
qemu_init_vcpu(cs);
tcc->parent_realize(dev, errp);
}
CPUSPARCState *cpu_sparc_init(const char *cpu_model)
{
CPUSPARCState *env;
env = g_new0(CPUSPARCState, 1);
cpu_exec_init(env);
gen_intermediate_code_init(env);
if (cpu_sparc_register(env, cpu_model) < 0) {
cpu_sparc_close(env);
return NULL;
}
qemu_init_vcpu(env);
return env;
}
static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
qemu_init_vcpu(cs);
cpu_reset(cs);
ncc->parent_realize(dev, errp);
}
static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
qemu_init_vcpu(cs);
xcc->parent_realize(dev, errp);
}
int resume_all_vcpus(struct uc_struct *uc)
{
CPUState *cpu = uc->cpu;
// Fix call multiple time (vu).
// We have to check whether this is the second time, then reset all CPU.
if (!cpu->created) {
cpu->created = true;
cpu->halted = 0;
if (qemu_init_vcpu(cpu))
return -1;
}
//qemu_clock_enable(QEMU_CLOCK_VIRTUAL, true);
cpu_resume(cpu);
qemu_tcg_cpu_loop(uc);
return 0;
}
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
riscv_cpu_register_gdb_regs_for_features(cs);
qemu_init_vcpu(cs);
cpu_reset(cs);
mcc->parent_realize(dev, errp);
}
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
MIPSCPU *cpu = MIPS_CPU(dev);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
}
cpu_mips_realize_env(&cpu->env);
cpu_reset(cs);
qemu_init_vcpu(cs);
mcc->parent_realize(dev, errp);
}
CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
{
UniCore32CPU *cpu;
CPUUniCore32State *env;
static int inited = 1;
if (object_class_by_name(cpu_model) == NULL) {
return NULL;
}
cpu = UNICORE32_CPU(object_new(cpu_model));
env = &cpu->env;
if (inited) {
inited = 0;
uc32_translate_init();
}
qemu_init_vcpu(env);
return env;
}
