/** * Check if the requested number of dwords is available in the CS and * if not, flush. * \param r300 The context. * \param flags See r300_prepare_flags. * \param cs_dwords The number of dwords to reserve in CS. * \return TRUE if the CS was flushed */ static boolean r300_reserve_cs_dwords(struct r300_context *r300, enum r300_prepare_flags flags, unsigned cs_dwords) { boolean flushed = FALSE; boolean emit_states = flags & PREP_EMIT_STATES; boolean emit_vertex_arrays = flags & PREP_EMIT_VARRAYS; boolean emit_vertex_arrays_swtcl = flags & PREP_EMIT_VARRAYS_SWTCL; /* Add dirty state, index offset, and AOS. */ if (emit_states) cs_dwords += r300_get_num_dirty_dwords(r300); if (r300->screen->caps.is_r500) cs_dwords += 2; /* emit_index_offset */ if (emit_vertex_arrays) cs_dwords += 55; /* emit_vertex_arrays */ if (emit_vertex_arrays_swtcl) cs_dwords += 7; /* emit_vertex_arrays_swtcl */ cs_dwords += r300_get_num_cs_end_dwords(r300); /* Reserve requested CS space. */ if (cs_dwords > (RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw)) { r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL); flushed = TRUE; } return flushed; }
/** * Check if the requested number of dwords is available in the CS and * if not, flush. * \param r300 The context. * \param flags See r300_prepare_flags. * \param cs_dwords The number of dwords to reserve in CS. * \return TRUE if the CS was flushed */ static boolean r300_reserve_cs_dwords(struct r300_context *r300, enum r300_prepare_flags flags, unsigned cs_dwords) { boolean flushed = FALSE; boolean first_draw = flags & PREP_FIRST_DRAW; boolean emit_aos = flags & PREP_EMIT_AOS; boolean emit_aos_swtcl = flags & PREP_EMIT_AOS_SWTCL; boolean hw_index_bias = r500_index_bias_supported(r300); /* Add dirty state, index offset, and AOS. */ if (first_draw) { cs_dwords += r300_get_num_dirty_dwords(r300); if (hw_index_bias) cs_dwords += 2; /* emit_index_offset */ if (emit_aos) cs_dwords += 55; /* emit_aos */ if (emit_aos_swtcl) cs_dwords += 7; /* emit_aos_swtcl */ } cs_dwords += r300_get_num_cs_end_dwords(r300); /* Reserve requested CS space. */ if (cs_dwords > (r300->cs->ndw - r300->cs->cdw)) { r300->context.flush(&r300->context, 0, NULL); flushed = TRUE; } return flushed; }
/* Clear currently bound buffers. */ static void r300_clear(struct pipe_context* pipe, unsigned buffers, const union pipe_color_union *color, double depth, unsigned stencil) { /* My notes about Zbuffer compression: * * 1) The zbuffer must be micro-tiled and whole microtiles must be * written if compression is enabled. If microtiling is disabled, * it locks up. * * 2) There is ZMASK RAM which contains a compressed zbuffer. * Each dword of the Z Mask contains compression information * for 16 4x4 pixel tiles, that is 2 bits for each tile. * On chips with 2 Z pipes, every other dword maps to a different * pipe. On newer chipsets, there is a new compression mode * with 8x8 pixel tiles per 2 bits. * * 3) The FASTFILL bit has nothing to do with filling. It only tells hw * it should look in the ZMASK RAM first before fetching from a real * zbuffer. * * 4) If a pixel is in a cleared state, ZB_DEPTHCLEARVALUE is returned * during zbuffer reads instead of the value that is actually stored * in the zbuffer memory. A pixel is in a cleared state when its ZMASK * is equal to 0. Therefore, if you clear ZMASK with zeros, you may * leave the zbuffer memory uninitialized, but then you must enable * compression, so that the ZMASK RAM is actually used. * * 5) Each 4x4 (or 8x8) tile is automatically decompressed and recompressed * during zbuffer updates. A special decompressing operation should be * used to fully decompress a zbuffer, which basically just stores all * compressed tiles in ZMASK to the zbuffer memory. * * 6) For a 16-bit zbuffer, compression causes a hung with one or * two samples and should not be used. * * 7) FORCE_COMPRESSED_STENCIL_VALUE should be enabled for stencil clears * to avoid needless decompression. * * 8) Fastfill must not be used if reading of compressed Z data is disabled * and writing of compressed Z data is enabled (RD/WR_COMP_ENABLE), * i.e. it cannot be used to compress the zbuffer. * * 9) ZB_CB_CLEAR does not interact with zbuffer compression in any way. * * - Marek */ struct r300_context* r300 = r300_context(pipe); struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; struct r300_hyperz_state *hyperz = (struct r300_hyperz_state*)r300->hyperz_state.state; uint32_t width = fb->width; uint32_t height = fb->height; uint32_t hyperz_dcv = hyperz->zb_depthclearvalue; /* Enable fast Z clear. * The zbuffer must be in micro-tiled mode, otherwise it locks up. */ if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { boolean zmask_clear, hiz_clear; zmask_clear = r300_fast_zclear_allowed(r300); hiz_clear = r300_hiz_clear_allowed(r300); /* If we need Hyper-Z. */ if (zmask_clear || hiz_clear) { r300->num_z_clears++; /* Try to obtain the access to Hyper-Z buffers if we don't have one. */ if (!r300->hyperz_enabled) { r300->hyperz_enabled = r300->rws->cs_request_feature(r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, TRUE); if (r300->hyperz_enabled) { /* Need to emit HyperZ buffer regs for the first time. */ r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG); } } /* Setup Hyper-Z clears. */ if (r300->hyperz_enabled) { DBG(r300, DBG_HYPERZ, "r300: Clear memory: %s%s\n", zmask_clear ? "ZMASK " : "", hiz_clear ? "HIZ" : ""); if (zmask_clear) { hyperz_dcv = hyperz->zb_depthclearvalue = r300_depth_clear_value(fb->zsbuf->format, depth, stencil); r300_mark_atom_dirty(r300, &r300->zmask_clear); buffers &= ~PIPE_CLEAR_DEPTHSTENCIL; } if (hiz_clear) { r300->hiz_clear_value = r300_hiz_clear_value(depth); r300_mark_atom_dirty(r300, &r300->hiz_clear); } } } } /* Enable CBZB clear. */ if (r300_cbzb_clear_allowed(r300, buffers)) { struct r300_surface *surf = r300_surface(fb->cbufs[0]); hyperz->zb_depthclearvalue = r300_depth_clear_cb_value(surf->base.format, color->f); width = surf->cbzb_width; height = surf->cbzb_height; r300->cbzb_clear = TRUE; r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG); } /* Clear. */ if (buffers) { enum pipe_format cformat = fb->nr_cbufs ? fb->cbufs[0]->format : PIPE_FORMAT_NONE; /* Clear using the blitter. */ r300_blitter_begin(r300, R300_CLEAR); util_blitter_clear(r300->blitter, width, height, fb->nr_cbufs, buffers, cformat, color, depth, stencil); r300_blitter_end(r300); } else if (r300->zmask_clear.dirty || r300->hiz_clear.dirty) { /* Just clear zmask and hiz now, this does not use the standard draw * procedure. */ /* Calculate zmask_clear and hiz_clear atom sizes. */ unsigned dwords = (r300->zmask_clear.dirty ? r300->zmask_clear.size : 0) + (r300->hiz_clear.dirty ? r300->hiz_clear.size : 0) + r300_get_num_cs_end_dwords(r300); /* Reserve CS space. */ if (dwords > (RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw)) { r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL); } /* Emit clear packets. */ if (r300->zmask_clear.dirty) { r300_emit_zmask_clear(r300, r300->zmask_clear.size, r300->zmask_clear.state); r300->zmask_clear.dirty = FALSE; } if (r300->hiz_clear.dirty) { r300_emit_hiz_clear(r300, r300->hiz_clear.size, r300->hiz_clear.state); r300->hiz_clear.dirty = FALSE; } } else { assert(0); } /* Disable CBZB clear. */ if (r300->cbzb_clear) { r300->cbzb_clear = FALSE; hyperz->zb_depthclearvalue = hyperz_dcv; r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG); } /* Enable fastfill and/or hiz. * * If we cleared zmask/hiz, it's in use now. The Hyper-Z state update * looks if zmask/hiz is in use and programs hardware accordingly. */ if (r300->zmask_in_use || r300->hiz_in_use) { r300_mark_atom_dirty(r300, &r300->hyperz_state); } }
/* Clear currently bound buffers. */ static void r300_clear(struct pipe_context* pipe, unsigned buffers, const float* rgba, double depth, unsigned stencil) { /* My notes about fastfill: * * 1) Only the zbuffer is cleared. * * 2) The zbuffer must be micro-tiled and whole microtiles must be * written. If microtiling is disabled, it locks up. * * 3) There is Z Mask RAM which contains a compressed zbuffer and * it interacts with fastfill. We should figure out how to use it * to get more performance. * This is what we know about the Z Mask: * * Each dword of the Z Mask contains compression information * for 16 4x4 pixel blocks, that is 2 bits for each block. * On chips with 2 Z pipes, every other dword maps to a different * pipe. * * 4) ZB_DEPTHCLEARVALUE is used to clear the zbuffer and the Z Mask must * be equal to 0. (clear the Z Mask RAM with zeros) * * 5) For 16-bit zbuffer, compression causes a hung with one or * two samples and should not be used. * * 6) FORCE_COMPRESSED_STENCIL_VALUE should be enabled for stencil clears * to avoid needless decompression. * * 7) Fastfill must not be used if reading of compressed Z data is disabled * and writing of compressed Z data is enabled (RD/WR_COMP_ENABLE), * i.e. it cannot be used to compress the zbuffer. * * 8) ZB_CB_CLEAR does not interact with fastfill in any way. * * - Marek */ struct r300_context* r300 = r300_context(pipe); struct pipe_framebuffer_state *fb = (struct pipe_framebuffer_state*)r300->fb_state.state; struct r300_hyperz_state *hyperz = (struct r300_hyperz_state*)r300->hyperz_state.state; struct r300_texture *zstex = fb->zsbuf ? r300_texture(fb->zsbuf->texture) : NULL; uint32_t width = fb->width; uint32_t height = fb->height; boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ); uint32_t hyperz_dcv = hyperz->zb_depthclearvalue; /* Enable fast Z clear. * The zbuffer must be in micro-tiled mode, otherwise it locks up. */ if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && can_hyperz) { hyperz_dcv = hyperz->zb_depthclearvalue = r300_depth_clear_value(fb->zsbuf->format, depth, stencil); r300_mark_fb_state_dirty(r300, R300_CHANGED_ZCLEAR_FLAG); if (zstex->zmask_mem[fb->zsbuf->u.tex.level]) { r300_mark_atom_dirty(r300, &r300->zmask_clear); buffers &= ~PIPE_CLEAR_DEPTHSTENCIL; } if (zstex->hiz_mem[fb->zsbuf->u.tex.level]) r300_mark_atom_dirty(r300, &r300->hiz_clear); } /* Enable CBZB clear. */ if (r300_cbzb_clear_allowed(r300, buffers)) { struct r300_surface *surf = r300_surface(fb->cbufs[0]); hyperz->zb_depthclearvalue = r300_depth_clear_cb_value(surf->base.format, rgba); width = surf->cbzb_width; height = surf->cbzb_height; r300->cbzb_clear = TRUE; r300_mark_fb_state_dirty(r300, R300_CHANGED_CBZB_FLAG); } /* Clear. */ if (buffers) { /* Clear using the blitter. */ r300_blitter_begin(r300, R300_CLEAR); util_blitter_clear(r300->blitter, width, height, fb->nr_cbufs, buffers, rgba, depth, stencil); r300_blitter_end(r300); } else if (r300->zmask_clear.dirty) { /* Just clear zmask and hiz now, this does not use a standard draw * procedure. */ unsigned dwords; /* Calculate zmask_clear and hiz_clear atom sizes. */ r300_update_hyperz_state(r300); dwords = r300->zmask_clear.size + (r300->hiz_clear.dirty ? r300->hiz_clear.size : 0) + r300_get_num_cs_end_dwords(r300); /* Reserve CS space. */ if (dwords > (R300_MAX_CMDBUF_DWORDS - r300->cs->cdw)) { r300->context.flush(&r300->context, 0, NULL); } /* Emit clear packets. */ r300_emit_zmask_clear(r300, r300->zmask_clear.size, r300->zmask_clear.state); r300->zmask_clear.dirty = FALSE; if (r300->hiz_clear.dirty) { r300_emit_hiz_clear(r300, r300->hiz_clear.size, r300->hiz_clear.state); r300->hiz_clear.dirty = FALSE; } } else { assert(0); } /* Disable CBZB clear. */ if (r300->cbzb_clear) { r300->cbzb_clear = FALSE; hyperz->zb_depthclearvalue = hyperz_dcv; r300_mark_fb_state_dirty(r300, R300_CHANGED_CBZB_FLAG); } /* Enable fastfill and/or hiz. * * If we cleared zmask/hiz, it's in use now. The Hyper-Z state update * looks if zmask/hiz is in use and enables fastfill accordingly. */ if (zstex && (zstex->zmask_in_use[fb->zsbuf->u.tex.level] || zstex->hiz_in_use[fb->zsbuf->u.tex.level])) { r300_mark_atom_dirty(r300, &r300->hyperz_state); } }
static void r300_render_draw_elements(struct vbuf_render* render, const ushort* indices, uint count) { struct r300_render* r300render = r300_render(render); struct r300_context* r300 = r300render->r300; int i; unsigned end_cs_dwords; unsigned max_index = (r300->draw_vbo_size - r300->draw_vbo_offset) / (r300render->r300->vertex_info.size * 4) - 1; unsigned short_count; unsigned free_dwords; CS_LOCALS(r300); DBG(r300, DBG_DRAW, "r300: render_draw_elements (count: %d)\n", count); if (r300->draw_first_emitted) { if (!r300_prepare_for_rendering(r300, PREP_EMIT_STATES | PREP_EMIT_VARRAYS_SWTCL | PREP_INDEXED, NULL, 256, 0, 0, -1)) return; } else { if (!r300_emit_states(r300, PREP_EMIT_STATES | PREP_EMIT_VARRAYS_SWTCL | PREP_INDEXED, NULL, 0, 0, -1)) return; } /* Below we manage the CS space manually because there may be more * indices than it can fit in CS. */ end_cs_dwords = r300_get_num_cs_end_dwords(r300); while (count) { free_dwords = RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw; short_count = MIN2(count, (free_dwords - end_cs_dwords - 6) * 2); BEGIN_CS(6 + (short_count+1)/2); OUT_CS_REG(R300_GA_COLOR_CONTROL, r300_provoking_vertex_fixes(r300, r300render->prim)); OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, max_index); OUT_CS_PKT3(R300_PACKET3_3D_DRAW_INDX_2, (short_count+1)/2); OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (short_count << 16) | r300render->hwprim); for (i = 0; i < short_count-1; i += 2) { OUT_CS(indices[i+1] << 16 | indices[i]); } if (short_count % 2) { OUT_CS(indices[short_count-1]); } END_CS; /* OK now subtract the emitted indices and see if we need to emit * another draw packet. */ indices += short_count; count -= short_count; if (count) { if (!r300_prepare_for_rendering(r300, PREP_EMIT_VARRAYS_SWTCL | PREP_INDEXED, NULL, 256, 0, 0, -1)) return; end_cs_dwords = r300_get_num_cs_end_dwords(r300); } } r300->draw_first_emitted = TRUE; }