static u8 fw_iocmd_write(struct _adapter *pAdapter,
struct IOCMD_STRUCT iocmd, u32 value)
{
u32 cmd32 = 0;
u8 iocmd_class = iocmd.cmdclass;
u32 iocmd_value = iocmd.value;
u8 iocmd_idx = iocmd.index;
r8712_fw_cmd_data(pAdapter, &value, 0);
msleep(100);
cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
return r8712_fw_cmd(pAdapter, cmd32);
}
/*
* Special for bb and rf reg read/write
*/
static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
{
u32 cmd32 = 0, val32 = 0;
u8 iocmd_class = iocmd.cmdclass;
u16 iocmd_value = iocmd.value;
u8 iocmd_idx = iocmd.index;
cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
if (r8712_fw_cmd(pAdapter, cmd32))
r8712_fw_cmd_data(pAdapter, &val32, 1);
else
val32 = 0;
return val32;
}
static void enable_video_mode(struct _adapter *padapter, int cbw40_value)
{
/* bit 8:
* 1 -> enable video mode to 96B AP
* 0 -> disable video mode to 96B AP
* bit 9:
* 1 -> enable 40MHz mode
* 0 -> disable 40MHz mode
* bit 10:
* 1 -> enable STBC
* 0 -> disable STBC
*/
u32 intcmd = 0xf4000500; /* enable bit8, bit10*/
if (cbw40_value) {
/* if the driver supports the 40M bandwidth,
* we can enable the bit 9.*/
intcmd |= 0x200;
}
r8712_fw_cmd(padapter, intcmd);
}
