static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
#endif
}
/* this function must be called with interrupt disabled */
static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
unsigned long reg)
{
u16 tmp;
tmp = r8a66597_read(r8a66597, INTENB0);
r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE, INTENB0);
r8a66597_bclr(r8a66597, 1 << pipenum, reg);
r8a66597_write(r8a66597, tmp, INTENB0);
}
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
if (r8a66597->pdata->on_chip) {
clk_disable_unprepare(r8a66597->clk);
} else {
r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
}
}
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
if (r8a66597->pdata->on_chip) {
#ifdef CONFIG_HAVE_CLK
clk_disable(r8a66597->clk);
#endif
} else {
r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
}
}
static int send_status_packet(struct r8a66597 *r8a66597,
unsigned long pipe)
{
r8a66597_bset(r8a66597, SQSET, DCPCTR);
r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR);
if (usb_pipein(pipe)) {
r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG);
r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
r8a66597_write(r8a66597, BCLR | BVAL, CFIFOCTR);
} else {
r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
r8a66597_write(r8a66597, BCLR, CFIFOCTR);
}
r8a66597_mdfy(r8a66597, PID_BUF, PID, DCPCTR);
while (!(r8a66597_read(r8a66597, BEMPSTS) & 0x0001))
if (ctrlc())
return -1;
return 0;
}
static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
{
u16 val, tmp;
r8a66597_write(r8a66597, 0, get_intenb_reg(port));
r8a66597_write(r8a66597, 0, get_intsts_reg(port));
r8a66597_port_power(r8a66597, port, 0);
do {
tmp = r8a66597_read(r8a66597, SOFCFG) & EDGESTS;
udelay(640);
} while (tmp == EDGESTS);
val = port ? DRPD : DCFM | DRPD;
r8a66597_bclr(r8a66597, val, get_syscfg_reg(port));
r8a66597_bclr(r8a66597, HSE, get_syscfg_reg(port));
}
static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
{
u16 tmp;
int i = 0;
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
do {
r8a66597_write(r8a66597, SCKE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & SCKE) != SCKE);
r8a66597_write(r8a66597, 0x04, 0x02);
#else
do {
r8a66597_write(r8a66597, USBE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
#if !defined(CONFIG_RZA_USB)
r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
i = 0;
r8a66597_bset(r8a66597, XCKE, SYSCFG0);
do {
udelay(1000);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 500) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & SCKE) != SCKE);
#else
/*
* RZ/A Only:
* Bits XTAL(UCKSEL) and UPLLE in SYSCFG0 for USB0 controls both USB0
* and USB1, so we must always set the USB0 register
*/
#if (CONFIG_R8A66597_XTAL == 1)
setbits(le16, R8A66597_BASE0, XTAL);
#endif
mdelay(1);
setbits(le16, R8A66597_BASE0, UPLLE);
mdelay(1);
r8a66597_bset(r8a66597, SUSPM, SUSPMODE0);
#endif /* CONFIG_RZA_USB */
#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
return 0;
}
static void r8a66597_enable_port(struct r8a66597 *r8a66597, int port)
{
u16 val;
val = port ? DRPD : DCFM | DRPD;
r8a66597_bset(r8a66597, val, get_syscfg_reg(port));
r8a66597_bset(r8a66597, HSE, get_syscfg_reg(port));
r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR, get_dmacfg_reg(port));
r8a66597_bclr(r8a66597, DTCHE, get_intenb_reg(port));
r8a66597_bset(r8a66597, ATTCHE, get_intenb_reg(port));
}
/* this function must be called with interrupt disabled */
static void clear_all_buffer(struct r8a66597 *r8a66597,
struct r8a66597_pipe *pipe)
{
u16 tmp;
if (!pipe || pipe->info.pipenum == 0)
return;
pipe_stop(r8a66597, pipe);
r8a66597_bset(r8a66597, ACLRM, pipe->pipectr);
tmp = r8a66597_read(r8a66597, pipe->pipectr);
tmp = r8a66597_read(r8a66597, pipe->pipectr);
tmp = r8a66597_read(r8a66597, pipe->pipectr);
r8a66597_bclr(r8a66597, ACLRM, pipe->pipectr);
}
static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
{
u16 tmp;
int i = 0;
if (r8a66597->pdata->on_chip) {
#ifdef CONFIG_HAVE_CLK
clk_enable(r8a66597->clk);
#endif
do {
r8a66597_write(r8a66597, SCKE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printk(KERN_ERR "r8a66597: reg access fail.\n");
return -ENXIO;
}
} while ((tmp & SCKE) != SCKE);
r8a66597_write(r8a66597, 0x04, 0x02);
} else {
do {
r8a66597_write(r8a66597, USBE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printk(KERN_ERR "r8a66597: reg access fail.\n");
return -ENXIO;
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
XTAL, SYSCFG0);
i = 0;
r8a66597_bset(r8a66597, XCKE, SYSCFG0);
do {
msleep(1);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 500) {
printk(KERN_ERR "r8a66597: reg access fail.\n");
return -ENXIO;
}
} while ((tmp & SCKE) != SCKE);
}
return 0;
}
static int receive_control_packet(struct r8a66597 *r8a66597,
struct usb_device *dev,
void *buffer, int transfer_len)
{
u16 tmp;
int rcv_len;
/* FIXME: limit transfer size : 64byte or less */
r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG);
r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
r8a66597_bset(r8a66597, SQSET, DCPCTR);
r8a66597_write(r8a66597, BCLR, CFIFOCTR);
r8a66597_mdfy(r8a66597, PID_BUF, PID, DCPCTR);
while (!(r8a66597_read(r8a66597, BRDYSTS) & 0x0001))
if (ctrlc())
return -1;
r8a66597_write(r8a66597, ~0x0001, BRDYSTS);
r8a66597_mdfy(r8a66597, MBW, MBW | CURPIPE, CFIFOSEL);
r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0);
tmp = r8a66597_read(r8a66597, CFIFOCTR);
if ((tmp & FRDY) == 0) {
printf("%s FRDY is not set. (%x)\n", __func__, tmp);
return -1;
}
rcv_len = tmp & DTLN;
dev->act_len += rcv_len;
r8a66597_mdfy(r8a66597, PID_NAK, PID, DCPCTR);
if (buffer) {
if (rcv_len == 0)
r8a66597_write(r8a66597, BCLR, DCPCTR);
else
r8a66597_read_fifo(r8a66597, CFIFO, buffer, rcv_len);
}
return 0;
}
static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
{
u16 tmp;
int i = 0;
#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
do {
r8a66597_write(r8a66597, SCKE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & SCKE) != SCKE);
r8a66597_write(r8a66597, 0x04, 0x02);
#else
do {
r8a66597_write(r8a66597, USBE, SYSCFG0);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 1000) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & USBE) != USBE);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0);
i = 0;
r8a66597_bset(r8a66597, XCKE, SYSCFG0);
do {
udelay(1000);
tmp = r8a66597_read(r8a66597, SYSCFG0);
if (i++ > 500) {
printf("register access fail.\n");
return -1;
}
} while ((tmp & SCKE) != SCKE);
#endif /* #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) */
return 0;
}
static void pipe_buffer_setting(struct r8a66597 *r8a66597,
struct usb_device *dev, unsigned long pipe)
{
u16 val = 0;
u16 pipenum, bufnum, maxpacket;
if (usb_pipein(pipe)) {
pipenum = BULK_IN_PIPENUM;
bufnum = BULK_IN_BUFNUM;
maxpacket = dev->epmaxpacketin[usb_pipeendpoint(pipe)];
} else {
pipenum = BULK_OUT_PIPENUM;
bufnum = BULK_OUT_BUFNUM;
maxpacket = dev->epmaxpacketout[usb_pipeendpoint(pipe)];
}
if (r8a66597->pipe_config & (1 << pipenum))
return;
r8a66597->pipe_config |= (1 << pipenum);
r8a66597_bset(r8a66597, ACLRM, get_pipectr_addr(pipenum));
r8a66597_bclr(r8a66597, ACLRM, get_pipectr_addr(pipenum));
r8a66597_write(r8a66597, pipenum, PIPESEL);
/* FIXME: This driver support bulk transfer only. */
if (!usb_pipein(pipe))
val |= R8A66597_DIR;
else
val |= R8A66597_SHTNAK;
val |= R8A66597_BULK | R8A66597_DBLB | usb_pipeendpoint(pipe);
r8a66597_write(r8a66597, val, PIPECFG);
r8a66597_write(r8a66597, (8 << 10) | bufnum, PIPEBUF);
r8a66597_write(r8a66597, make_devsel(usb_pipedevice(pipe)) |
maxpacket, PIPEMAXP);
r8a66597_write(r8a66597, 0, PIPEPERI);
r8a66597_write(r8a66597, SQCLR, get_pipectr_addr(pipenum));
}
/* this function must be called with interrupt disabled */
static void pipe_buffer_setting(struct r8a66597 *r8a66597,
struct r8a66597_pipe_info *info)
{
u16 val = 0;
if (info->pipenum == 0)
return;
r8a66597_bset(r8a66597, ACLRM, get_pipectr_addr(info->pipenum));
r8a66597_bclr(r8a66597, ACLRM, get_pipectr_addr(info->pipenum));
r8a66597_write(r8a66597, info->pipenum, PIPESEL);
if (!info->dir_in)
val |= R8A66597_DIR;
if (info->type == R8A66597_BULK && info->dir_in)
val |= R8A66597_DBLB | R8A66597_SHTNAK;
val |= info->type | info->epnum;
r8a66597_write(r8a66597, val, PIPECFG);
r8a66597_write(r8a66597, (info->buf_bsize << 10) | (info->bufnum),
PIPEBUF);
r8a66597_write(r8a66597, make_devsel(info->address) | info->maxpacket,
PIPEMAXP);
r8a66597_write(r8a66597, info->interval, PIPEPERI);
}
static void r8a66597_clock_disable(struct r8a66597 *r8a66597)
{
#if !defined(CONFIG_RZA_USB)
r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
udelay(1);
#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
#endif
#else
r8a66597_bclr(r8a66597, SUSPM, SUSPMODE0);
clrbits(le16, R8A66597_BASE0, UPLLE);
mdelay(1);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);
mdelay(1);
#endif
}
