static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC PC\n"
/* syntax not yet supported */
// "=SP &PC1\n"
"=A0 r0\n"
"=A1 r1\n"
"=A2 r2\n"
"=A3 r3\n"
"=R0 r0\n"
"gpr r0 .4 0 0\n"
"gpr r1 .4 1 0\n"
"gpr r2 .4 2 0\n"
"gpr r3 .4 3 0\n"
"gpr r4 .4 4 0\n"
"gpr r5 .4 5 0\n"
"gpr r6 .4 6 0\n"
"gpr r7 .4 7 0\n"
"gpr r8 .4 8 0\n"
"gpr r9 .4 9 0\n"
"gpr r10 .4 10 0\n"
"gpr r11 .4 11 0\n"
"gpr r12 .4 12 0\n"
"gpr r13 .4 13 0\n"
"gpr r14 .4 14 0\n"
"gpr r15 .4 15 0\n"
"gpr PC .64 32 0\n"
/* stack */
"gpr PC1 .64 34 0\n"
"gpr PC2 .64 34 0\n"
"gpr PC3 .64 34 0\n"
;
return r_reg_set_profile_string (anal->reg, p);
}
/* Set the profile register */
static int sh_set_reg_profile(RAnal* anal){
//TODO Add system ( ssr, spc ) + fpu regs
int ret = r_reg_set_profile_string(anal->reg,
"=pc pc\n"
"=sp r15\n"
"=bp r14\n"
"gpr r0 .32 0 0\n"
"gpr r1 .32 4 0\n"
"gpr r2 .32 8 0\n"
"gpr r3 .32 12 0\n"
"gpr r4 .32 16 0\n"
"gpr r5 .32 20 0\n"
"gpr r6 .32 24 0\n"
"gpr r7 .32 28 0\n"
"gpr r8 .32 32 0\n"
"gpr r9 .32 36 0\n"
"gpr r10 .32 40 0\n"
"gpr r11 .32 44 0\n"
"gpr r12 .32 48 0\n"
"gpr r13 .32 52 0\n"
"gpr r14 .32 56 0\n"
"gpr r15 .32 60 0\n"
"gpr pc .32 64 0\n"
"gpr pr .32 68 0\n"
"gpr sr .32 72 0\n"
"gpr gbr .32 76 0\n"
"gpr mach .32 80 0\n"
"gpr macl .32 84 0\n"
);
return ret;
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC pc\n"
"gpr A .32 0 0\n"
"gpr X .32 4 0\n"
"gpr M[0] .32 8 0\n"
"gpr M[1] .32 12 0\n"
"gpr M[2] .32 16 0\n"
"gpr M[3] .32 20 0\n"
"gpr M[4] .32 24 0\n"
"gpr M[5] .32 28 0\n"
"gpr M[6] .32 32 0\n"
"gpr M[7] .32 36 0\n"
"gpr M[8] .32 40 0\n"
"gpr M[9] .32 44 0\n"
"gpr M[10] .32 48 0\n"
"gpr M[11] .32 52 0\n"
"gpr M[12] .32 56 0\n"
"gpr M[13] .32 60 0\n"
"gpr M[14] .32 64 0\n"
"gpr M[15] .32 68 0\n"
"gpr pc .32 72 0\n"
"gpr len .32 76 0\n"
"gpr R0 .32 80 0\n"
"gpr R1 .32 84 0\n"
"gpr R2 .32 88 0\n"
"gpr R3 .32 92 0\n"
"gpr R4 .32 96 0\n"
"gpr R5 .32 100 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
/* Set the profile register */
static int sh_set_reg_profile(RAnal* anal){
//TODO Add system ( ssr, spc ) + fpu regs
const char *p =
"=PC pc\n"
"=SP r15\n"
"=BP r14\n"
"gpr r0 .32 0 0\n"
"gpr r1 .32 4 0\n"
"gpr r2 .32 8 0\n"
"gpr r3 .32 12 0\n"
"gpr r4 .32 16 0\n"
"gpr r5 .32 20 0\n"
"gpr r6 .32 24 0\n"
"gpr r7 .32 28 0\n"
"gpr r8 .32 32 0\n"
"gpr r9 .32 36 0\n"
"gpr r10 .32 40 0\n"
"gpr r11 .32 44 0\n"
"gpr r12 .32 48 0\n"
"gpr r13 .32 52 0\n"
"gpr r14 .32 56 0\n"
"gpr r15 .32 60 0\n"
"gpr pc .32 64 0\n"
"gpr pr .32 68 0\n"
"gpr sr .32 72 0\n"
"gpr gbr .32 76 0\n"
"gpr mach .32 80 0\n"
"gpr macl .32 84 0\n";
return r_reg_set_profile_string(anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = NULL;
p =
"=pc pc\n"
"=sp r1\n"
"=sr srr1\n" // status register ??
"=a0 r3\n" // also for ret
"=a1 r4\n"
"=a2 r5\n"
"=a3 r6\n"
"=a4 r7\n"
"=a5 r8\n"
"=a6 r6\n"
"gpr srr0 .32 0 0\n"
"gpr srr1 .32 4 0\n"
"gpr r0 .32 8 0\n"
"gpr r1 .32 12 0\n"
"gpr r2 .32 16 0\n"
"gpr r3 .32 20 0\n"
"gpr r4 .32 24 0\n"
"gpr r5 .32 28 0\n"
"gpr r6 .32 32 0\n"
"gpr r7 .32 36 0\n"
"gpr r8 .32 40 0\n"
"gpr r9 .32 44 0\n"
"gpr r10 .32 48 0\n"
"gpr r11 .32 52 0\n"
"gpr r12 .32 56 0\n"
"gpr r13 .32 60 0\n"
"gpr r14 .32 64 0\n"
"gpr r15 .32 68 0\n"
"gpr r16 .32 72 0\n"
"gpr r17 .32 76 0\n"
"gpr r18 .32 80 0\n"
"gpr r19 .32 84 0\n"
"gpr r20 .32 88 0\n"
"gpr r21 .32 92 0\n"
"gpr r22 .32 96 0\n"
"gpr r23 .32 100 0\n"
"gpr r24 .32 104 0\n"
"gpr r25 .32 108 0\n"
"gpr r26 .32 112 0\n"
"gpr r27 .32 116 0\n"
"gpr r28 .32 120 0\n"
"gpr r29 .32 124 0\n"
"gpr r30 .32 128 0\n"
"gpr r31 .32 132 0\n"
"gpr cr .32 136 0\n"
"gpr xer .32 140 0\n"
"gpr lr .32 144 0\n"
"gpr ctr .32 148 0\n"
"gpr mq .32 152 0\n"
"gpr vrsave .32 156 0\n"
// extra
"gpr pc .32 160 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC pc\n"
"=SP sp\n"
"gpr r0 .8 0 0\n"
"gpr r1 .8 1 0\n"
"gpr r2 .8 2 0\n"
"gpr r3 .8 3 0\n"
"gpr r4 .8 4 0\n"
"gpr r5 .8 5 0\n"
"gpr r6 .8 6 0\n"
"gpr r7 .8 7 0\n"
"gpr a .8 8 0\n"
"gpr b .8 9 0\n"
"gpr dptr .16 10 0\n"
"gpr dpl .8 10 0\n"
"gpr dph .8 11 0\n"
"gpr psw .8 12 0\n"
"gpr p .1 .96 0\n"
"gpr ov .1 .98 0\n"
"gpr ac .1 .102 0\n"
"gpr c .1 .103 0\n"
"gpr sp .8 13 0\n"
"gpr pc .16 15 0\n"
// ---------------------------------------------------
// 8051 memory emulation control registers
// These registers map 8051 memory classes to r2's
// linear address space. Registers contain offset
// to r2 memory representing the memory class.
// Offsets are initialized based on asm.cpu, but can
// be updated with ar command.
//
// _code
// program memory (CODE)
// _idata
// internal data memory (IDATA, IRAM)
// _sfr
// special function registers (SFR)
// _xdata
// external data memory (XDATA, XRAM)
// _pdata
// page accessed by movx @ri op (PDATA, XREG)
// r2 addr = (_pdata & 0xff) << 8 + x_data
// if 0xffffffnn, addr = ([SFRnn] << 8) + _xdata (TODO)
"gpr _code .32 20 0\n"
"gpr _idata .32 24 0\n"
"gpr _sfr .32 28 0\n"
"gpr _xdata .32 32 0\n"
"gpr _pdata .32 36 0\n";
int retval = r_reg_set_profile_string (anal->reg, p);
if (retval) {
// reset emulation control registers based on cpu
set_cpu_model (anal, true);
}
return retval;
}
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=PC pc\n"
"=SP a7\n"
"=BP a6\n"
"=A0 a0\n"
"=A1 a1\n"
"=A2 a2\n"
"=A3 a3\n"
"gpr d0 .32 0 0\n"
"gpr d1 .32 4 0\n"
"gpr d2 .32 8 0\n"
"gpr d3 .32 12 0\n"
"gpr d4 .32 16 0\n"
"gpr d5 .32 20 0\n"
"gpr d6 .32 24 0\n"
"gpr d7 .32 28 0\n"
"gpr a0 .32 32 0\n"
"gpr a1 .32 36 0\n"
"gpr a2 .32 40 0\n"
"gpr a3 .32 44 0\n"
"gpr a4 .32 48 0\n"
"gpr a5 .32 52 0\n"
"gpr a6 .32 56 0\n"
"gpr a7 .32 60 0\n"
"gpr fp0 .32 64 0\n" //FPU register 0, 96bits to write and read max
"gpr fp1 .32 68 0\n" //FPU register 1, 96bits to write and read max
"gpr fp2 .32 72 0\n" //FPU register 2, 96bits to write and read max
"gpr fp3 .32 76 0\n" //FPU register 3, 96bits to write and read max
"gpr fp4 .32 80 0\n" //FPU register 4, 96bits to write and read max
"gpr fp5 .32 84 0\n" //FPU register 5, 96bits to write and read max
"gpr fp6 .32 88 0\n" //FPU register 6, 96bits to write and read max
"gpr fp7 .32 92 0\n" //FPU register 7, 96bits to write and read max
"gpr pc .32 96 0\n"
"gpr sr .32 100 0\n" //only available for read and write access during supervisor mode 16bit
"gpr ccr .32 104 0\n" //subset of the SR, available from any mode
"gpr sfc .32 108 0\n" //source function code register
"gpr dfc .32 112 0\n" //destination function code register
"gpr usp .32 116 0\n" //user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0
"gpr vbr .32 120 0\n" //vector base register, this is a Address pointer
"gpr cacr .32 124 0\n" //cache control register, implementation specific
"gpr caar .32 128 0\n" //cache address register, 68020, 68EC020, 68030 and 68EC030 only.
"gpr msp .32 132 0\n" //master stack pointer, this is an shadow register of A7 supervisor mode, SR bits 0xD && 0xC are set
"gpr isp .32 136 0\n" //interrupt stack pointer, this is an shadow register of A7 supervisor mode, SR bit 0xD is set, 0xC is not.
"gpr tc .32 140 0\n"
"gpr itt0 .32 144 0\n" //in 68EC040 this is IACR0
"gpr itt1 .32 148 0\n" //in 68EC040 this is IACR1
"gpr dtt0 .32 156 0\n" //in 68EC040 this is DACR0
"gpr dtt1 .32 160 0\n" //in 68EC040 this is DACR1
"gpr mmusr .32 164 0\n"
"gpr urp .32 168 0\n"
"gpr srp .32 172 0\n"
"gpr fpcr .32 176 0\n"
"gpr fpsr .32 180 0\n"
"gpr fpiar .32 184 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=PC pc\n"
"=SP sp\n"
"=A0 a0\n"
"=A1 a1\n"
"=A2 a2\n"
"=A3 a3\n"
"gpr d0 .32 0 0\n"
"gpr d1 .32 4 0\n"
"gpr d2 .32 8 0\n"
"gpr d3 .32 12 0\n"
"gpr d4 .32 16 0\n"
"gpr d5 .32 20 0\n"
"gpr d6 .32 24 0\n"
"gpr d7 .32 28 0\n"
"gpr a0 .32 32 0\n"
"gpr a1 .32 36 0\n"
"gpr a2 .32 40 0\n"
"gpr a3 .32 44 0\n"
"gpr a4 .32 48 0\n"
"gpr a5 .32 52 0\n"
"gpr a6 .32 56 0\n"
"gpr a7 .32 60 0\n"
"gpr fp0 .32 64 0\n"
"gpr fp1 .32 68 0\n"
"gpr fp2 .32 72 0\n"
"gpr fp3 .32 76 0\n"
"gpr fp4 .32 80 0\n"
"gpr fp5 .32 84 0\n"
"gpr fp6 .32 88 0\n"
"gpr fp7 .32 92 0\n"
"gpr pc .32 96 0\n"
"gpr sr .32 100 0\n"
"gpr ccr .32 104 0\n"
"gpr sfc .32 108 0\n"
"gpr dfc .32 112 0\n"
"gpr usp .32 116 0\n"
"gpr vbr .32 120 0\n"
"gpr cacr .32 124 0\n"
"gpr caar .32 128 0\n"
"gpr msp .32 132 0\n"
"gpr isp .32 136 0\n"
"gpr tc .32 140 0\n"
"gpr itt0 .32 144 0\n"
"gpr itt1 .32 148 0\n"
"gpr dtt0 .32 156 0\n"
"gpr dtt1 .32 160 0\n"
"gpr mmusr .32 164 0\n"
"gpr urp .32 168 0\n"
"gpr srp .32 172 0\n"
"gpr fpcr .32 176 0\n"
"gpr fpsr .32 180 0\n"
"gpr fpiar .32 184 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=pc pc\n"
"=sp stk\n"
"gpr pc .32 0 0\n"
"gpr stk .32 4 0\n"
"gpr zf .32 8 0\n"
"gpr sf .32 12 0\n"
"gpr gf .32 16 0\n"
"gpr r_00 .32 20 0\n"
"gpr r_01 .32 24 0\n"
"gpr r_02 .32 28 0\n"
"gpr r_03 .32 32 0\n"
"gpr r_04 .32 36 0\n"
"gpr r_05 .32 40 0\n"
"gpr r_06 .32 44 0\n"
"gpr r_07 .32 48 0\n"
"gpr r_08 .32 52 0\n"
"gpr r_09 .32 56 0\n"
"gpr r_0a .32 60 0\n"
"gpr r_0b .32 64 0\n"
"gpr r_0c .32 68 0\n"
"gpr r_0d .32 72 0\n"
"gpr r_0e .32 76 0\n"
"gpr r_0f .32 80 0\n"
"gpr r_10 .32 84 0\n"
"gpr r_11 .32 88 0\n"
"gpr r_12 .32 92 0\n"
"gpr r_13 .32 96 0\n"
"gpr r_14 .32 100 0\n"
"gpr r_15 .32 104 0\n"
"gpr r_16 .32 108 0\n"
"gpr r_17 .32 112 0\n"
"gpr r_18 .32 116 0\n"
"gpr r_19 .32 120 0\n"
"gpr r_1a .32 124 0\n"
"gpr r_1b .32 128 0\n"
"gpr r_1c .32 132 0\n"
"gpr r_1d .32 136 0\n"
"gpr r_1e .32 140 0\n"
"gpr r_1f .32 144 0\n"
"gpr r_20 .32 148 0\n"
"gpr r_21 .32 152 0\n"
"gpr r_22 .32 156 0\n"
"gpr r_23 .32 160 0\n"
"gpr r_24 .32 168 0\n"
"gpr r_25 .32 172 0\n"
"gpr r_26 .32 176 0\n"
"gpr r_27 .32 180 0\n"
"gpr r_28 .32 184 0\n"
"gpr r_29 .32 188 0\n"
"gpr r_data .32 192 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
// XXX
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=PC pc\n"
"=SP sp\n"
"=A0 a0\n"
"=A1 a1\n"
"gpr pc .16 48 0\n"
"gpr sp .16 48 0\n"
"gpr a0 .16 48 0\n"
"gpr a1 .16 48 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=PC pc\n"
"=SP y\n"
"=A0 r24\n"
"=A1 r25\n"
"=A2 r26\n"
"=A3 r27\n"
"gpr psr .32 0 0\n"
"gpr pc .32 4 0\n"
"gpr npc .32 8 0\n"
"gpr y .32 12 0\n"
/* r0-r7 are global aka g0-g7 */
"gpr r0 .32 16 0\n"
"gpr r1 .32 20 0\n"
"gpr r2 .32 24 0\n"
"gpr r3 .32 28 0\n"
"gpr r4 .32 32 0\n"
"gpr r5 .32 36 0\n"
"gpr r6 .32 40 0\n"
"gpr r7 .32 44 0\n"
/* r8-15 are out (o0-o7) */
"gpr r8 .32 48 0\n"
"gpr r9 .32 52 0\n"
"gpr r10 .32 56 0\n"
"gpr r11 .32 60 0\n"
"gpr r12 .32 64 0\n"
"gpr r13 .32 68 0\n"
"gpr r14 .32 72 0\n"
"gpr r15 .32 76 0\n"
/* r16-23 are local (o0-o7) */
"gpr r16 .32 80 0\n"
"gpr r17 .32 84 0\n"
"gpr r18 .32 88 0\n"
"gpr r19 .32 92 0\n"
"gpr r20 .32 96 0\n"
"gpr r21 .32 100 0\n"
"gpr r22 .32 104 0\n"
"gpr r23 .32 108 0\n"
/* r24-31 are in (i0-i7) */
"gpr r24 .32 112 0\n"
"gpr r25 .32 116 0\n"
"gpr r26 .32 120 0\n"
"gpr r27 .32 124 0\n"
"gpr r28 .32 128 0\n"
"gpr r29 .32 132 0\n"
"gpr r30 .32 136 0\n"
"gpr r31 .32 140 0\n"
;
return r_reg_set_profile_string (anal->reg, p);
}
static int py_set_reg_profile(RAnal *a) {
const char *profstr = "";
if (py_set_reg_profile_cb) {
PyObject *result = PyObject_CallObject (py_set_reg_profile_cb, NULL);
if (result) {
profstr = PyUnicode_AsUTF8 (result);
return r_reg_set_profile_string (a->reg, profstr);
} else {
eprintf ("Unknown type returned. String was expected.\n");
PyErr_Print();
}
}
return -1;
}
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=pc pc\n"
"=bp brk\n"
"=sp ptr\n"
"=a0 rax\n"
"=a1 rbx\n"
"=a2 rcx\n"
"=a3 rdx\n"
"gpr ptr .32 0 0\n" // data pointer
"gpr pc .32 4 0\n" // program counter
"gpr brk .32 8 0\n" // brackets
"gpr scr .32 12 0\n" // screen
"gpr kbd .32 16 0\n"; // keyboard
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = \
"=PC pc\n"
"=SP sp\n"
"=A0 A\n"
"=A1 C\n"
"=A2 G\n"
"=A3 T\n"
"gpr pc .64 0 0\n"
"gpr sp .64 8 0\n"
"gpr A .8 16 0\n"
"gpr C .8 17 0\n"
"gpr G .8 18 0\n"
"gpr T .8 19 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC ip\n"
"=SP sp\n"
"=BP bp\n"
"=A0 v0\n"
"=A1 v1\n"
"=A2 v2\n"
"=A3 v3\n"
"gpr v0 .32 0 0\n"
"gpr v1 .32 4 0\n"
"gpr v2 .32 8 0\n"
"gpr v3 .32 12 0\n"
"gpr ip .32 40 0\n"
"gpr sp .32 44 0\n"
;
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=pc ip\n"
"=sp sp\n"
"=bp bp\n"
"=a0 v0\n"
"=a1 v1\n"
"=a2 v2\n"
"=a3 v3\n"
"gpr v0 .32 0 0\n"
"gpr v1 .32 4 0\n"
"gpr v2 .32 8 0\n"
"gpr v3 .32 12 0\n"
"gpr ip .32 40 0\n"
"gpr sp .32 44 0\n"
;
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
// XXX : 64bit profile
char *p = "=pc pc\n"
"=sp sp\n"
"=a0 a0\n"
"=a1 a1\n"
"=a2 a2\n"
"=a3 a3\n"
"gpr zero .32 0 0\n"
"gpr at .32 4 0\n"
"gpr v0 .32 8 0\n"
"gpr v1 .32 12 0\n"
"gpr a0 .32 16 0\n"
"gpr a1 .32 20 0\n"
"gpr a2 .32 24 0\n"
"gpr a3 .32 28 0\n"
"gpr t0 .32 32 0\n"
"gpr t1 .32 36 0\n"
"gpr t2 .32 40 0\n"
"gpr t3 .32 44 0\n"
"gpr t4 .32 48 0\n"
"gpr t5 .32 52 0\n"
"gpr t6 .32 56 0\n"
"gpr t7 .32 60 0\n"
"gpr s0 .32 64 0\n"
"gpr s1 .32 68 0\n"
"gpr s2 .32 72 0\n"
"gpr s3 .32 76 0\n"
"gpr s4 .32 80 0\n"
"gpr s5 .32 84 0\n"
"gpr s6 .32 88 0\n"
"gpr s7 .32 92 0\n"
"gpr t8 .32 96 0\n"
"gpr t9 .32 100 0\n"
"gpr k0 .32 104 0\n"
"gpr k1 .32 108 0\n"
"gpr gp .32 112 0\n"
"gpr sp .32 116 0\n"
"gpr fp .32 120 0\n"
"gpr ra .32 124 0\n"
"gpr pc .32 128 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
R_API int r_reg_set_profile(RReg *reg, const char *profile) {
int ret;
char *base, *file;
char *str = r_file_slurp (profile, NULL);
if (!str) {
base = r_sys_getenv (R_LIB_ENV);
if (base) {
file = r_str_append (base, profile);
str = r_file_slurp (file, NULL);
free (file);
}
}
if (!str) {
eprintf ("r_reg_set_profile: Cannot find '%s'\n", profile);
return false;
}
ret = r_reg_set_profile_string (reg, str);
free (str);
return ret;
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC mpc\n"
"=SP sp\n"
"=A0 af\n"
"=A1 bc\n"
"=A2 de\n"
"=A3 hl\n"
"gpr mpc .32 0 0\n"
"gpr pc .16 0 0\n"
"gpr m .16 2 0\n"
"gpr sp .16 4 0\n"
"gpr af .16 6 0\n"
"gpr f .8 6 0\n"
"gpr a .8 7 0\n"
"gpr Z .1 .55 0\n"
"gpr N .1 .54 0\n"
"gpr H .1 .53 0\n"
"gpr C .1 .52 0\n"
"gpr bc .16 8 0\n"
"gpr c .8 8 0\n"
"gpr b .8 9 0\n"
"gpr de .16 10 0\n"
"gpr e .8 10 0\n"
"gpr d .8 11 0\n"
"gpr hl .16 12 0\n"
"gpr l .8 12 0\n"
"gpr h .8 13 0\n"
"gpr mbcrom .16 14 0\n"
"gpr mbcram .16 16 0\n"
"gpr ime .1 18 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC pc\n"
"=SP sp\n"
"gpr r0 .8 0 0\n"
"gpr r1 .8 1 0\n"
"gpr r2 .8 2 0\n"
"gpr r3 .8 3 0\n"
"gpr r4 .8 4 0\n"
"gpr r5 .8 5 0\n"
"gpr r6 .8 6 0\n"
"gpr r7 .8 7 0\n"
"gpr A .8 8 0\n"
"gpr B .8 9 0\n"
"gpr sp .8 10 0\n"
"gpr pc .16 12 0\n"
"gpr dptr .16 14 0\n"
"gpr C .1 16 0\n"
"gpr OV .1 17 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
char *p =
"=PC pc\n"
"=SP r7\n"
"gpr r0 .16 0 0\n"
"gpr r0h .8 0 0\n"
"gpr r0l .8 1 0\n"
"gpr r1 .16 2 0\n"
"gpr r1h .8 2 0\n"
"gpr r1l .8 3 0\n"
"gpr r2 .16 4 0\n"
"gpr r2h .8 4 0\n"
"gpr r2l .8 5 0\n"
"gpr r3 .16 6 0\n"
"gpr r3h .8 6 0\n"
"gpr r3l .8 7 0\n"
"gpr r4 .16 8 0\n"
"gpr r4h .8 8 0\n"
"gpr r4l .8 9 0\n"
"gpr r5 .16 10 0\n"
"gpr r5h .8 10 0\n"
"gpr r5l .8 11 0\n"
"gpr r6 .16 12 0\n"
"gpr r6h .8 12 0\n"
"gpr r6l .8 13 0\n"
"gpr r7 .16 14 0\n"
"gpr r7h .8 14 0\n"
"gpr r7l .8 15 0\n"
"gpr pc .16 16 0\n"
"gpr ccr .8 18 0\n"
"gpr I .1 .151 0\n"
"gpr U1 .1 .150 0\n"
"gpr H .1 .149 0\n"
"gpr U2 .1 .148 0\n"
"gpr N .1 .147 0\n"
"gpr Z .1 .146 0\n"
"gpr V .1 .145 0\n"
"gpr C .1 .144 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
char *p =
"=PC pc\n"
"=SP sp\n"
"gpr a .8 0 0\n"
"gpr x .8 1 0\n"
"gpr y .8 2 0\n"
"gpr flags .8 3 0\n"
"gpr C .1 .24 0\n"
"gpr Z .1 .25 0\n"
"gpr I .1 .26 0\n"
"gpr D .1 .27 0\n"
// bit 4 (.28) is NOT a real flag.
// "gpr B .1 .28 0\n"
// bit 5 (.29) is not used
"gpr V .1 .30 0\n"
"gpr N .1 .31 0\n"
"gpr sp .8 4 0\n"
"gpr pc .16 5 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
R_API int r_reg_set_profile(RReg *reg, const char *profile) {
int ret;
char *base, *file;
char *str = r_file_slurp (profile, NULL);
if (!str) {
// XXX we must define this varname in r_lib.h /compiletime/
base = r_sys_getenv ("LIBR_PLUGINS");
if (base) {
file = r_str_concat (base, profile);
str = r_file_slurp (file, NULL);
free (file);
}
}
if (!str) {
eprintf ("r_reg_set_profile: Cannot find '%s'\n", profile);
return false;
}
ret = r_reg_set_profile_string (reg, str);
free (str);
return ret;
}
static int set_reg_profile(RAnal *anal) {
const char *p =
"=PC pc\n"
"=SP r14\n" // XXX
"=BP srp\n" // XXX
"=A0 r0\n"
"=A1 r1\n"
"=A2 r2\n"
"=A3 r3\n"
"gpr sp .32 56 0\n" // r14
"gpr acr .32 60 0\n" // r15
"gpr pc .32 64 0\n" // r16 // out of context
"gpr srp .32 68 0\n" // like rbp on x86 // out of context
// GPR
"gpr r0 .32 0 0\n"
"gpr r1 .32 4 0\n"
"gpr r2 .32 8 0\n"
"gpr r3 .32 12 0\n"
"gpr r4 .32 16 0\n"
"gpr r5 .32 20 0\n"
"gpr r6 .32 24 0\n"
"gpr r7 .32 28 0\n"
"gpr r8 .32 32 0\n"
"gpr r9 .32 36 0\n"
"gpr r10 .32 40 0\n"
"gpr r11 .32 44 0\n"
"gpr r12 .32 48 0\n"
"gpr r13 .32 52 0\n"
// STACK POINTER
"gpr r14 .32 56 0\n"
"gpr r15 .32 60 0\n"
// ADD P REGISTERS
;
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p;
p = "=PC pc\n"
"=SP r1\n"
"=SR sr\n"
"=A0 r3\n"
"=A1 r4\n"
"=A2 r5\n"
"=A3 r6\n"
"=A4 r7\n"
"=A5 r8\n"
"=A6 r6\n"
"gpr r0 .32 0 0\n"
"gpr r1 .32 4 0\n"
"gpr r2 .32 8 0\n"
"gpr r3 .32 12 0\n"
"gpr r4 .32 16 0\n"
"gpr r5 .32 20 0\n"
"gpr r6 .32 24 0\n"
"gpr r7 .32 28 0\n"
"gpr r8 .32 32 0\n"
"gpr r9 .32 36 0\n"
"gpr r10 .32 40 0\n"
"gpr r11 .32 44 0\n"
"gpr r12 .32 48 0\n"
"gpr r13 .32 52 0\n"
"gpr r14 .32 56 0\n"
"gpr r15 .32 60 0\n"
"gpr psr .32 64 0\n"
"gpr vbr .32 68 0\n"
"gpr epsr .32 72 0\n"
"gpr fpsr .32 76 0\n"
"gpr epc .32 80 0\n"
"gpr fpc .32 84 0\n"
"gpr ss0 .32 88 0\n"
"gpr ss1 .32 92 0\n"
"gpr ss2 .32 96 0\n"
"gpr ss3 .32 100 0\n"
"gpr ss4 .32 104 0\n"
"gpr gcr .32 108 0\n"
"gpr gsr .32 112 0\n"
"gpr cpidr .32 116 0\n"
"gpr dcsr .32 120 0\n"
"gpr cwr .32 124 0\n"
"gpr cr16 .32 128 0\n"
"gpr cfr .32 132 0\n"
"gpr ccr .32 136 0\n"
"gpr capr .32 140 0\n"
"gpr pacr .32 144 0\n"
"gpr prsr .32 148 0\n"
"gpr cr22 .32 152 0\n"
"gpr cr23 .32 156 0\n"
"gpr cr24 .32 160 0\n"
"gpr cr25 .32 164 0\n"
"gpr cr26 .32 168 0\n"
"gpr cr27 .32 172 0\n"
"gpr cr28 .32 176 0\n"
"gpr cr29 .32 180 0\n"
"gpr cr30 .32 184 0\n"
"gpr cr31 .32 188 0\n"
"gpr pc .32 192 0\n";
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = NULL;
if (anal->bits == 32) {
p =
"=PC pc\n"
"=SP r1\n"
"=SR srr1\n" // status register ??
"=A0 r3\n" // also for ret
"=A1 r4\n"
"=A2 r5\n"
"=A3 r6\n"
"=A4 r7\n"
"=A5 r8\n"
"=A6 r6\n"
"gpr srr0 .32 0 0\n"
"gpr srr1 .32 4 0\n"
"gpr r0 .32 8 0\n"
"gpr r1 .32 12 0\n"
"gpr r2 .32 16 0\n"
"gpr r3 .32 20 0\n"
"gpr r4 .32 24 0\n"
"gpr r5 .32 28 0\n"
"gpr r6 .32 32 0\n"
"gpr r7 .32 36 0\n"
"gpr r8 .32 40 0\n"
"gpr r9 .32 44 0\n"
"gpr r10 .32 48 0\n"
"gpr r11 .32 52 0\n"
"gpr r12 .32 56 0\n"
"gpr r13 .32 60 0\n"
"gpr r14 .32 64 0\n"
"gpr r15 .32 68 0\n"
"gpr r16 .32 72 0\n"
"gpr r17 .32 76 0\n"
"gpr r18 .32 80 0\n"
"gpr r19 .32 84 0\n"
"gpr r20 .32 88 0\n"
"gpr r21 .32 92 0\n"
"gpr r22 .32 96 0\n"
"gpr r23 .32 100 0\n"
"gpr r24 .32 104 0\n"
"gpr r25 .32 108 0\n"
"gpr r26 .32 112 0\n"
"gpr r27 .32 116 0\n"
"gpr r28 .32 120 0\n"
"gpr r29 .32 124 0\n"
"gpr r30 .32 128 0\n"
"gpr r31 .32 132 0\n"
"gpr lr .32 136 0\n"
"gpr ctr .32 140 0\n"
"gpr msr .32 144 0\n"
"gpr pc .32 148 0\n"
"gpr cr .64 152 0\n"
"gpr cr0 .8 152 0\n"
"gpr cr1 .8 153 0\n"
"gpr cr2 .8 154 0\n"
"gpr cr3 .8 155 0\n"
"gpr cr4 .8 156 0\n"
"gpr cr5 .8 157 0\n"
"gpr cr6 .8 158 0\n"
"gpr cr7 .8 159 0\n"
"gpr xer .32 160 0\n"
"gpr mq .32 164 0\n"
"gpr fpscr .32 168 0\n"
"gpr vrsave .32 172 0\n"
"gpr pvr .32 176 0\n"
"gpr dccr .32 180 0\n"
"gpr iccr .32 184 0\n"
"gpr dear .32 188 0\n"
"gpr hid0 .32 192 0\n"
"gpr hid1 .32 196 0\n"
"gpr hid2 .32 200 0\n"
"gpr hid3 .32 204 0\n"
"gpr hid4 .32 208 0\n"
"gpr hid5 .32 212 0\n"
"gpr hid6 .32 216 0\n"
"gpr ibat0 .64 220 0\n"
"gpr ibat1 .64 228 0\n"
"gpr ibat2 .64 236 0\n"
"gpr ibat3 .64 244 0\n"
"gpr ibat0l .32 220 0\n"
"gpr ibat1l .32 228 0\n"
"gpr ibat2l .32 236 0\n"
"gpr ibat3l .32 244 0\n"
"gpr ibat0u .32 224 0\n"
"gpr ibat1u .32 232 0\n"
"gpr ibat2u .32 240 0\n"
"gpr ibat3u .32 248 0\n"
"gpr dbat0 .64 256 0\n"
"gpr dbat1 .64 264 0\n"
"gpr dbat2 .64 272 0\n"
"gpr dbat3 .64 280 0\n"
"gpr dbat0l .32 256 0\n"
"gpr dbat1l .32 264 0\n"
"gpr dbat2l .32 272 0\n"
"gpr dbat3l .32 280 0\n"
"gpr dbat0u .32 260 0\n"
"gpr dbat1u .32 268 0\n"
"gpr dbat2u .32 276 0\n"
"gpr dbat3u .32 284 0\n"
"gpr mask .32 288 0\n";
} else {
p =
"=PC pc\n"
"=SP r1\n"
"=SR srr1\n" // status register ??
"=A0 r3\n" // also for ret
"=A1 r4\n"
"=A2 r5\n"
"=A3 r6\n"
"=A4 r7\n"
"=A5 r8\n"
"=A6 r6\n"
"gpr srr0 .64 0 0\n"
"gpr srr1 .64 8 0\n"
"gpr r0 .64 16 0\n"
"gpr r1 .64 24 0\n"
"gpr r2 .64 32 0\n"
"gpr r3 .64 40 0\n"
"gpr r4 .64 48 0\n"
"gpr r5 .64 56 0\n"
"gpr r6 .64 64 0\n"
"gpr r7 .64 72 0\n"
"gpr r8 .64 80 0\n"
"gpr r9 .64 88 0\n"
"gpr r10 .64 96 0\n"
"gpr r11 .64 104 0\n"
"gpr r12 .64 112 0\n"
"gpr r13 .64 120 0\n"
"gpr r14 .64 128 0\n"
"gpr r15 .64 136 0\n"
"gpr r16 .64 144 0\n"
"gpr r17 .64 152 0\n"
"gpr r18 .64 160 0\n"
"gpr r19 .64 168 0\n"
"gpr r20 .64 176 0\n"
"gpr r21 .64 184 0\n"
"gpr r22 .64 192 0\n"
"gpr r23 .64 200 0\n"
"gpr r24 .64 208 0\n"
"gpr r25 .64 216 0\n"
"gpr r26 .64 224 0\n"
"gpr r27 .64 232 0\n"
"gpr r28 .64 240 0\n"
"gpr r29 .64 248 0\n"
"gpr r30 .64 256 0\n"
"gpr r31 .64 264 0\n"
"gpr lr .64 272 0\n"
"gpr ctr .64 280 0\n"
"gpr msr .64 288 0\n"
"gpr pc .64 296 0\n"
"gpr cr .64 304 0\n"
"gpr cr0 .8 304 0\n"
"gpr cr1 .8 305 0\n"
"gpr cr2 .8 306 0\n"
"gpr cr3 .8 307 0\n"
"gpr cr4 .8 308 0\n"
"gpr cr5 .8 309 0\n"
"gpr cr6 .8 310 0\n"
"gpr cr7 .8 311 0\n"
"gpr xer .64 312 0\n"
"gpr mq .64 320 0\n"
"gpr fpscr .64 328 0\n"
"gpr vrsave .64 336 0\n"
"gpr pvr .64 344 0\n"
"gpr dccr .32 352 0\n"
"gpr iccr .32 356 0\n"
"gpr dear .32 360 0\n"
"gpr hid0 .64 364 0\n"
"gpr hid1 .64 372 0\n"
"gpr hid2 .64 380 0\n"
"gpr hid3 .64 388 0\n"
"gpr hid4 .64 396 0\n"
"gpr hid5 .64 404 0\n"
"gpr hid6 .64 412 0\n"
"gpr ibat0 .64 420 0\n"
"gpr ibat1 .64 428 0\n"
"gpr ibat2 .64 436 0\n"
"gpr ibat3 .64 444 0\n"
"gpr ibat0l .32 420 0\n"
"gpr ibat1l .32 428 0\n"
"gpr ibat2l .32 436 0\n"
"gpr ibat3l .32 444 0\n"
"gpr ibat0u .32 424 0\n"
"gpr ibat1u .32 432 0\n"
"gpr ibat2u .32 440 0\n"
"gpr ibat3u .32 448 0\n"
"gpr dbat0 .64 456 0\n"
"gpr dbat1 .64 464 0\n"
"gpr dbat2 .64 472 0\n"
"gpr dbat3 .64 480 0\n"
"gpr dbat0l .32 456 0\n"
"gpr dbat1l .32 464 0\n"
"gpr dbat2l .32 472 0\n"
"gpr dbat3l .32 480 0\n"
"gpr dbat0u .32 460 0\n"
"gpr dbat1u .32 468 0\n"
"gpr dbat2u .32 476 0\n"
"gpr dbat3u .32 484 0\n"
"gpr mask .64 488 0\n"; //not a real register used on complex functions
}
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
const char *p = NULL;
switch (anal->bits) {
case 16: p=
"=pc ip\n"
"=sp sp\n"
"=bp bp\n"
"=a0 ax\n"
"=a1 bx\n"
"=a2 cx\n"
"=a3 di\n"
"gpr ip .16 48 0\n"
"gpr ax .16 24 0\n"
"gpr ah .8 25 0\n"
"gpr al .8 24 0\n"
"gpr bx .16 0 0\n"
"gpr bh .8 1 0\n"
"gpr bl .8 0 0\n"
"gpr cx .16 4 0\n"
"gpr ch .8 5 0\n"
"gpr cl .8 4 0\n"
"gpr dx .16 8 0\n"
"gpr dh .8 9 0\n"
"gpr dl .8 8 0\n"
"gpr sp .16 60 0\n"
"gpr bp .16 20 0\n"
"gpr si .16 12 0\n"
"gpr di .16 16 0\n"
"seg cs .16 52 0\n"
"gpr flags .16 56 0\n"
"gpr cf .1 .448 0\n"
"flg pf .1 .449 0\n"
"flg af .1 .450 0\n"
"gpr zf .1 .451 0\n"
"gpr sf .1 .452 0\n"
"flg tf .1 .453 0\n"
"flg if .1 .454 0\n"
"flg df .1 .455 0\n"
"flg of .1 .456 0\n"
"flg rf .1 .457 0\n";
#if 0
"drx dr0 .32 0 0\n"
"drx dr1 .32 4 0\n"
"drx dr2 .32 8 0\n"
"drx dr3 .32 12 0\n"
//"drx dr4 .32 16 0\n"
//"drx dr5 .32 20 0\n"
"drx dr6 .32 24 0\n"
"drx dr7 .32 28 0\n"
#endif
break;
case 32: p=
"=pc eip\n"
"=sp esp\n"
"=bp ebp\n"
"=a0 eax\n"
"=a1 ebx\n"
"=a2 ecx\n"
"=a3 edi\n"
"gpr oeax .32 44 0\n"
"gpr eax .32 24 0\n"
"gpr ax .16 24 0\n"
"gpr ah .8 25 0\n"
"gpr al .8 24 0\n"
"gpr ebx .32 0 0\n"
"gpr bx .16 0 0\n"
"gpr bh .8 1 0\n"
"gpr bl .8 0 0\n"
"gpr ecx .32 4 0\n"
"gpr cx .16 4 0\n"
"gpr ch .8 5 0\n"
"gpr cl .8 4 0\n"
"gpr edx .32 8 0\n"
"gpr dx .16 8 0\n"
"gpr dh .8 9 0\n"
"gpr dl .8 8 0\n"
"gpr esi .32 12 0\n"
"gpr si .16 12 0\n"
"gpr edi .32 16 0\n"
"gpr di .16 16 0\n"
"gpr esp .32 60 0\n"
"gpr sp .16 60 0\n"
"gpr ebp .32 20 0\n"
"gpr bp .16 20 0\n"
"gpr eip .32 48 0\n"
"gpr ip .16 48 0\n"
"seg xfs .32 36 0\n"
"seg xgs .32 40 0\n"
"seg xcs .32 52 0\n"
"seg cs .16 52 0\n"
"seg xss .32 52 0\n"
"gpr eflags .32 56 0 c1p.a.zstido.n.rv\n"
"gpr flags .16 56 0\n"
"gpr cf .1 .448 0\n"
"flg pf .1 .449 0\n"
"flg af .1 .450 0\n"
"gpr zf .1 .451 0\n"
"gpr sf .1 .452 0\n"
"flg tf .1 .453 0\n"
"flg if .1 .454 0\n"
"flg df .1 .455 0\n"
"flg of .1 .456 0\n"
"flg rf .1 .457 0\n"
"drx dr0 .32 0 0\n"
"drx dr1 .32 4 0\n"
"drx dr2 .32 8 0\n"
"drx dr3 .32 12 0\n"
//"drx dr4 .32 16 0\n"
//"drx dr5 .32 20 0\n"
"drx dr6 .32 24 0\n"
"drx dr7 .32 28 0\n";
break;
case 64:
p =
"=pc rip\n"
"=sp rsp\n"
"=bp rbp\n"
"=a0 rdi\n"
"=a1 rsi\n"
"=a2 rdx\n"
"=a3 r10\n"
"=a4 r8\n"
"=a5 r9\n"
"=sn rax\n"
"# no profile defined for x86-64\n"
"gpr rax .64 80 0\n"
"gpr eax .32 80 0\n"
"gpr ax .16 80 0\n"
"gpr ah .8 81 0\n"
"gpr al .8 80 0\n"
"gpr rbx .64 40 0\n"
"gpr ebx .32 40 0\n"
"gpr bx .16 40 0\n"
"gpr bh .8 41 0\n"
"gpr bl .8 40 0\n"
"gpr rcx .64 88 0\n"
"gpr ecx .32 88 0\n"
"gpr cx .16 88 0\n"
"gpr ch .8 89 0\n"
"gpr cl .8 88 0\n"
"gpr rdx .64 96 0\n"
"gpr edx .32 96 0\n"
"gpr dx .16 96 0\n"
"gpr dh .8 97 0\n"
"gpr dl .8 96 0\n"
"gpr rsi .64 104 0\n"
"gpr esi .32 104 0\n"
"gpr si .16 104 0\n"
"gpr sil .8 104 0\n"
"gpr sih .8 105 0\n"
"gpr rdi .64 112 0\n"
"gpr edi .32 112 0\n"
"gpr di .16 112 0\n"
"gpr dil .8 112 0\n"
"gpr dih .8 113 0\n"
"gpr r8 .64 72 0\n"
"gpr r8d .32 72 0\n"
"gpr r8w .16 72 0\n"
"gpr r8b .8 72 0\n"
"gpr r9 .64 64 0\n"
"gpr r9d .32 64 0\n"
"gpr r9w .16 64 0\n"
"gpr r9b .8 64 0\n"
"gpr r10 .64 56 0\n"
"gpr r10d .32 56 0\n"
"gpr r10w .16 56 0\n"
"gpr r10b .8 56 0\n"
"gpr r11 .64 48 0\n"
"gpr r11d .32 48 0\n"
"gpr r11w .16 48 0\n"
"gpr r11b .8 48 0\n"
"gpr r12 .64 24 0\n"
"gpr r12d .32 24 0\n"
"gpr r12w .16 24 0\n"
"gpr r12b .8 24 0\n"
"gpr r13 .64 16 0\n"
"gpr r13d .32 16 0\n"
"gpr r13w .16 16 0\n"
"gpr r13b .8 16 0\n"
"gpr r14 .64 8 0\n"
"gpr r14d .32 8 0\n"
"gpr r14w .16 8 0\n"
"gpr r14b .8 8 0\n"
"gpr r15 .64 0 0\n"
"gpr r15d .32 0 0\n"
"gpr r15w .16 0 0\n"
"gpr r15b .8 0 0\n"
"gpr rip .64 128 0\n"
"gpr rbp .64 32 0\n"
"gpr ebp .32 32 0\n"
"gpr bp .16 32 0\n"
"seg cs .64 136 0\n"
"gpr rflags .64 144 0 c1p.a.zstido.n.rv\n"
"gpr eflags .32 144 0 c1p.a.zstido.n.rv\n"
"gpr cf .1 .1152 0 carry\n"
"gpr pf .1 .1154 0 parity\n"
"gpr af .1 .1156 0 adjust\n"
"gpr zf .1 .1158 0 zero\n"
"gpr sf .1 .1159 0 sign\n"
"gpr tf .1 .1160 0 trap\n"
"gpr if .1 .1161 0 interrupt\n"
"gpr df .1 .1162 0 direction\n"
"gpr of .1 .1163 0 overflow\n"
"gpr rsp .64 152 0\n"
"seg ss .64 160 0\n"
"seg fs_base .64 168 0\n"
"seg gs_base .64 176 0\n"
"seg ds .64 184 0\n"
"seg es .64 192 0\n"
"seg fs .64 200 0\n"
"seg gs .64 208 0\n"
"drx dr0 .64 0 0\n"
"drx dr1 .64 8 0\n"
"drx dr2 .64 16 0\n"
"drx dr3 .64 24 0\n"
// dr4 32
// dr5 40
"drx dr6 .64 48 0\n"
"drx dr7 .64 56 0\n"
/*0030 struct user_fpregs_struct
0031 {
0032 __uint16_t cwd;
0033 __uint16_t swd;
0034 __uint16_t ftw;
0035 __uint16_t fop;
0036 __uint64_t rip;
0037 __uint64_t rdp;
0038 __uint32_t mxcsr;
0039 __uint32_t mxcr_mask;
0040 __uint32_t st_space[32]; // 8*16 bytes for each FP-reg = 128 bytes
0041 __uint32_t xmm_space[64]; // 16*16 bytes for each XMM-reg = 256 bytes
0042 __uint32_t padding[24];
0043 };
*/
"fpu cwd .16 0 0\n"
"fpu swd .16 2 0\n"
"fpu ftw .16 4 0\n"
"fpu fop .16 6 0\n"
"fpu frip .64 8 0\n"
"fpu frdp .64 16 0\n"
"fpu mxcsr .32 24 0\n"
"fpu mxcr_mask .32 28 0\n"
"fpu st0 .64 32 0\n"
"fpu st1 .64 48 0\n"
"fpu st2 .64 64 0\n"
"fpu st3 .64 80 0\n"
"fpu st4 .64 96 0\n"
"fpu st5 .64 112 0\n"
"fpu st6 .64 128 0\n"
"fpu st7 .64 144 0\n"
"fpu xmm0h .64 160 0\n"
"fpu xmm0l .64 168 0\n"
"fpu xmm1h .64 176 0\n"
"fpu xmm1l .64 184 0\n"
"fpu xmm2h .64 192 0\n"
"fpu xmm2l .64 200 0\n"
"fpu xmm3h .64 208 0\n"
"fpu xmm3l .64 216 0\n"
"fpu xmm4h .64 224 0\n"
"fpu xmm4l .64 232 0\n"
"fpu xmm5h .64 240 0\n"
"fpu xmm5l .64 248 0\n"
"fpu xmm6h .64 256 0\n"
"fpu xmm6l .64 264 0\n"
"fpu xmm7h .64 272 0\n"
"fpu xmm7l .64 280 0\n"
"fpu x64 .64 288 0\n";
break;
#if 0
default: p= /* XXX */
"=pc rip\n"
"=sp rsp\n"
"=bp rbp\n"
"=a0 rax\n"
"=a1 rbx\n"
"=a2 rcx\n"
"=a3 rdx\n"
"# no profile defined for x86-64\n"
"gpr r15 .64 0 0\n"
"gpr r14 .64 8 0\n"
"gpr r13 .64 16 0\n"
"gpr r12 .64 24 0\n"
"gpr rbp .64 32 0\n"
"gpr ebp .32 32 0\n"
"gpr rbx .64 40 0\n"
"gpr ebx .32 40 0\n"
"gpr bx .16 40 0\n"
"gpr bh .8 41 0\n"
"gpr bl .8 40 0\n"
"gpr r11 .64 48 0\n"
"gpr r10 .64 56 0\n"
"gpr r9 .64 64 0\n"
"gpr r8 .64 72 0\n"
"gpr rax .64 80 0\n"
"gpr eax .32 80 0\n"
"gpr rcx .64 88 0\n"
"gpr ecx .32 88 0\n"
"gpr rdx .64 96 0\n"
"gpr edx .32 96 0\n"
"gpr rsi .64 104 0\n"
"gpr esi .32 104 0\n"
"gpr rdi .64 112 0\n"
"gpr edi .32 112 0\n"
"gpr oeax .64 120 0\n"
"gpr rip .64 128 0\n"
"seg cs .64 136 0\n"
//"flg eflags .64 144 0\n"
"gpr eflags .32 144 0 c1p.a.zstido.n.rv\n"
"gpr cf .1 .1152 0\n"
"flg pf .1 .1153 0\n"
"flg af .1 .1154 0\n"
"gpr zf .1 .1155 0\n"
"gpr sf .1 .1156 0\n"
"flg tf .1 .1157 0\n"
"flg if .1 .1158 0\n"
"flg df .1 .1159 0\n"
"flg of .1 .1160 0\n"
"flg rf .1 .1161 0\n"
"gpr rsp .64 152 0\n"
"seg ss .64 160 0\n"
"seg fs_base .64 168 0\n"
"seg gs_base .64 176 0\n"
"seg ds .64 184 0\n"
"seg es .64 192 0\n"
"seg fs .64 200 0\n"
"seg gs .64 208 0\n"
"drx dr0 .32 0 0\n"
"drx dr1 .32 4 0\n"
"drx dr2 .32 8 0\n"
"drx dr3 .32 12 0\n"
"drx dr6 .32 24 0\n"
"drx dr7 .32 28 0\n";
break;
#endif
}
return r_reg_set_profile_string (anal->reg, p);
}
static int set_reg_profile(RAnal *anal) {
/* XXX Dupped Profiles */
switch (anal->bits) {
case 16:
case 32:
return r_reg_set_profile_string (anal->reg,
"=pc r15\n"
"=sp r14\n" // XXX
"=bp r14\n" // XXX
"=a0 r0\n"
"=a1 r1\n"
"=a2 r2\n"
"=a3 r3\n"
"gpr lr .32 56 0\n" // r14
"gpr pc .32 60 0\n" // r15
"gpr r0 .32 0 0\n"
"gpr r1 .32 4 0\n"
"gpr r2 .32 8 0\n"
"gpr r3 .32 12 0\n"
"gpr r4 .32 16 0\n"
"gpr r5 .32 20 0\n"
"gpr r6 .32 24 0\n"
"gpr r7 .32 28 0\n"
"gpr r8 .32 32 0\n"
"gpr r9 .32 36 0\n"
"gpr r10 .32 40 0\n"
"gpr r11 .32 44 0\n"
"gpr r12 .32 48 0\n"
"gpr r13 .32 52 0\n"
"gpr r14 .32 56 0\n"
"gpr r15 .32 60 0\n"
"gpr r16 .32 64 0\n"
"gpr r17 .32 68 0\n");
case 64:
return r_reg_set_profile_string (anal->reg,
"=pc pc\n"
"=sp sp\n" // XXX
"=a0 x0\n"
"=a1 x1\n"
"=a2 x2\n"
"=a3 x3\n"
"=zf zf\n"
"=sf nf\n"
"=of vf\n"
"=cf cf\n"
"=sn ox0\n"
"gpr x0 .64 0 0\n" // x0
"gpr x1 .64 8 0\n" // x0
"gpr x2 .64 16 0\n" // x0
"gpr x3 .64 24 0\n" // x0
"gpr x4 .64 32 0\n" // x0
"gpr x5 .64 40 0\n" // x0
"gpr x6 .64 48 0\n" // x0
"gpr x7 .64 56 0\n" // x0
"gpr x8 .64 64 0\n" // x0
"gpr x9 .64 72 0\n" // x0
"gpr x10 .64 80 0\n" // x0
"gpr x11 .64 88 0\n" // x0
"gpr x12 .64 96 0\n" // x0
"gpr x13 .64 104 0\n" // x0
"gpr x14 .64 112 0\n" // x0
"gpr x15 .64 120 0\n" // x0
"gpr x16 .64 128 0\n" // x0
"gpr x17 .64 136 0\n" // x0
"gpr x18 .64 144 0\n" // x0
"gpr x19 .64 152 0\n" // x0
"gpr x20 .64 160 0\n" // x0
"gpr x21 .64 168 0\n" // x0
"gpr x22 .64 176 0\n" // x0
"gpr x23 .64 184 0\n" // x0
"gpr x24 .64 192 0\n" // x0
"gpr x25 .64 200 0\n" // x0
"gpr x26 .64 208 0\n" // x0
"gpr x27 .64 216 0\n" // x0
"gpr x28 .64 224 0\n" // x0
"gpr x29 .64 232 0\n" // x0
"gpr x30 .64 240 0\n" // x0
"gpr pc .64 248 0\n" // x0
"gpr pstate .64 256 0\n" // x0
"gpr ox0 .64 264 0\n" // x0
"gpr snr .64 272 0\n" // x0
// probably wrong
"gpr nf .1 .256 0 sign\n" // msb bit of last op
"gpr zf .1 .257 0 zero\n" // set if last op is 0
"gpr cf .1 .258 0 carry\n" // set if last op carries
"gpr vf .1 .515 0 overflow\n" // set if overflows
);
break;
}
return 0;
}
static int set_reg_profile(RAnal *anal) {
/* XXX Dupped Profiles */
if (anal->bits == 32)
#if __WINDOWS__
return r_reg_set_profile_string (anal->reg,
"=pc eip\n"
"=sp esp\n"
"=bp ebp\n"
"=a0 eax\n"
"=a1 ebx\n"
"=a2 ecx\n"
"=a3 edi\n"
"drx dr0 .32 4 0\n"
"drx dr1 .32 8 0\n"
"drx dr2 .32 12 0\n"
"drx dr3 .32 16 0\n"
"drx dr6 .32 20 0\n"
"drx dr7 .32 24 0\n"
/* floating save area 4+4+4+4+4+4+4+80+4 = 112 */
"seg gs .32 132 0\n"
"seg fs .32 136 0\n"
"seg es .32 140 0\n"
"seg ds .32 144 0\n"
"gpr edi .32 156 0\n"
"gpr esi .32 160 0\n"
"gpr ebx .32 164 0\n"
"gpr edx .32 168 0\n"
"gpr ecx .32 172 0\n"
"gpr eax .32 176 0\n"
"gpr ebp .32 180 0\n"
"gpr esp .32 196 0\n"
"gpr eip .32 184 0\n"
"seg cs .32 184 0\n"
"seg ds .32 152 0\n"
"seg gs .32 140 0\n"
"seg fs .32 144 0\n"
"gpr eflags .32 192 0 c1p.a.zstido.n.rv\n" // XXX must be flg
"seg ss .32 200 0\n"
/* +512 bytes for maximum supoprted extension extended registers */
);
#else
return r_reg_set_profile_string (anal->reg,
"=pc eip\n"
"=sp esp\n"
"=bp ebp\n"
"=a0 eax\n"
"=a1 ebx\n"
"=a2 ecx\n"
"=a3 edi\n"
"gpr eip .32 48 0\n"
"gpr ip .16 48 0\n"
"gpr oeax .32 44 0\n"
"gpr eax .32 24 0\n"
"gpr ax .16 24 0\n"
"gpr ah .8 24 0\n"
"gpr al .8 25 0\n"
"gpr ebx .32 0 0\n"
"gpr bx .16 0 0\n"
"gpr bh .8 0 0\n"
"gpr bl .8 1 0\n"
"gpr ecx .32 4 0\n"
"gpr cx .16 4 0\n"
"gpr ch .8 4 0\n"
"gpr cl .8 5 0\n"
"gpr edx .32 8 0\n"
"gpr dx .16 8 0\n"
"gpr dh .8 8 0\n"
"gpr dl .8 9 0\n"
"gpr esp .32 60 0\n"
"gpr sp .16 60 0\n"
"gpr ebp .32 20 0\n"
"gpr bp .16 20 0\n"
"gpr esi .32 12 0\n"
"gpr si .16 12 0\n"
"gpr edi .32 16 0\n"
"gpr di .16 16 0\n"
"seg xfs .32 36 0\n"
"seg xgs .32 40 0\n"
"seg xcs .32 52 0\n"
"seg cs .16 52 0\n"
"seg xss .32 52 0\n"
"gpr eflags .32 56 0 c1p.a.zstido.n.rv\n"
"gpr flags .16 56 0\n"
"flg carry .1 .448 0\n"
"flg flag_p .1 .449 0\n"
"flg flag_a .1 .450 0\n"
"flg zero .1 .451 0\n"
"flg sign .1 .452 0\n"
"flg flag_t .1 .453 0\n"
"flg flag_i .1 .454 0\n"
"flg flag_d .1 .455 0\n"
"flg flag_o .1 .456 0\n"
"flg flag_r .1 .457 0\n"
"drx dr0 .32 0 0\n"
"drx dr1 .32 4 0\n"
"drx dr2 .32 8 0\n"
"drx dr3 .32 12 0\n"
//"drx dr4 .32 16 0\n"
//"drx dr5 .32 20 0\n"
"drx dr6 .32 24 0\n"
"drx dr7 .32 28 0\n");
#endif
else return r_reg_set_profile_string (anal->reg,
