void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulCompareMatchValue;
const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;
/* Disable CMI2 and CMI3 interrupts. */
VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL );
/* Cancel CMT stop state in LPC. */
r_rst_write_enable();
MSTP( CMT1 ) = 0U;
r_rst_write_disable();
/* Interrupt on compare match. */
CMT2.CMCR.BIT.CMIE = 1;
CMT3.CMCR.BIT.CMIE = 1;
/* Calculate the compare match value. */
ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;
ulCompareMatchValue /= ulCMTClockDivider;
ulCompareMatchValue /= tmrCMT_1_CHANNEL_0_HZ;
ulCompareMatchValue -= 1UL;
CMT2.CMCOR = ( unsigned short ) ulCompareMatchValue;
ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;
ulCompareMatchValue /= ulCMTClockDivider;
ulCompareMatchValue /= tmrCMT_1_CHANNEL_1_HZ;
ulCompareMatchValue -= 1UL;
CMT3.CMCOR = ( unsigned short ) ulCompareMatchValue;
/* Divide the PCLK by 8. */
CMT2.CMCR.BIT.CKS = 0;
CMT3.CMCR.BIT.CKS = 0;
/* Clear count to 0. */
CMT2.CMCNT = 0;
CMT3.CMCNT = 0;
/* Set CMI2 and CMI3 edge detection type. */
VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );
/* Set CMI2 and CMI3 priority levels so they nest. */
VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2;
VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9;
/* Set CMI2 and CMI3 interrupt address. */
VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry;
VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry;
/* Enable CMI2 and CMI3 interrupts in ICU. */
VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );
/* Start CMT1 channel 0 and 1 count. */
CMT.CMSTR1.BIT.STR2 = 1U;
CMT.CMSTR1.BIT.STR3 = 1U;
}
/*
* The application must provide a function that configures a peripheral to
* create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT()
* in FreeRTOSConfig.h to call the function.
*/
void vConfigureTickInterrupt( void )
{
uint32_t ulCompareMatchValue;
const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;
/* Disable CMI5 interrupt. */
VIC.IEC9.LONG = 0x00001000UL;
/* Cancel CMT stop state in LPC. */
r_rst_write_enable();
MSTP( CMT2 ) = 0U;
r_rst_write_disable();
/* Interrupt on compare match. */
CMT5.CMCR.BIT.CMIE = 1;
/* Calculate the compare match value. */
ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;
ulCompareMatchValue /= ulCMTClockDivider;
ulCompareMatchValue /= configTICK_RATE_HZ;
ulCompareMatchValue -= 1UL;
/* Set the compare match value. */
CMT5.CMCOR = ( unsigned short ) ulCompareMatchValue;
/* Divide the PCLK by 8. */
CMT5.CMCR.BIT.CKS = 0;
CMT5.CMCNT = 0;
/* Set CMI5 edge detection type. */
VIC.PLS9.LONG |= 0x00001000UL;
/* Set CMI5 priority level to the lowest possible. */
VIC.PRL300.LONG = _CMT_PRIORITY_LEVEL31;
/* Set CMI5 interrupt address */
VIC.VAD300.LONG = ( uint32_t ) FreeRTOS_Tick_Handler_Entry;
/* Enable CMI5 interrupt in ICU. */
VIC.IEN9.LONG |= 0x00001000UL;
/* Start CMT5 count. */
CMT.CMSTR2.BIT.STR5 = 1U;
}
/*******************************************************************************
* Function Name : R_CPG_PLL_Wait
* Description : Wait about 100us for PLL stabilization by using CMT0
* Arguments : none
* Return Value : none
*******************************************************************************/
void R_CPG_PLL_Wait(void)
{
/* Enables writing to the registers related to Reset and Low-Power function */
r_rst_write_enable();
/* Release from the CMT0 module-stop state */
MSTP(CMT0) = 0;
/* Disables writing to the registers related to Reset and Low-Power function */
r_rst_write_disable();
/* Set CMT0 to 100us interval operation */
CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32
CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt
CMT0.CMCNT = CPG_CMT_REG_CLEAR; // Clear CMCNT counter
CMT0.CMCOR = CPG_CMT0_CONST_100_us; // Set constant value for 100us
/* Set IRQ21(CMI0) for polloing sequence */
VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt
VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt
VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
/* Enable IRQ interrupt (Clear CPSR.I bit to 0) */
asm("cpsie i"); // Clear CPSR.I bit to 0
asm("isb"); // Ensuring Context-changing
/* Start CMT0 count */
CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START;
/* Wait for 100us (IRQ21 is generated) */
while ( !(VIC.RAIS0.BIT.RAI21) )
{
/* Wait */
}
/* Stop CMT0 count */
CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP;
/* Initialize CMT0 settings and clear interrupt detection edge */
CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR;
CMT0.CMCNT = CPG_CMT_REG_CLEAR;
CMT0.CMCOR = CPG_CMT_REG_CLEAR;
CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR;
VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge
/* Disable IRQ interrupt (Set CPSR.I bit to 1) */
asm("cpsid i");
asm("isb");
/* Enables writing to the registers related to Reset and Low-Power function */
r_rst_write_enable();
/* Set CMT0 to module-stop state */
MSTP(CMT0) = 1;
/* Disables writing to the registers related to Reset and Low-Power function */
r_rst_write_disable();
}
