static void flush_prims( radeonContextPtr rmesa )
{
int i,j;
struct radeon_dma_region tmp = rmesa->dma.current;
tmp.buf->refcount++;
tmp.aos_size = rmesa->vb.vertex_size;
tmp.aos_stride = rmesa->vb.vertex_size;
tmp.aos_start = GET_START(&tmp);
rmesa->dma.current.ptr = rmesa->dma.current.start +=
(rmesa->vb.initial_counter - rmesa->vb.counter) * rmesa->vb.vertex_size * 4;
rmesa->tcl.vertex_format = rmesa->vb.vertex_format;
rmesa->tcl.aos_components[0] = &tmp;
rmesa->tcl.nr_aos_components = 1;
rmesa->dma.flush = NULL;
/* Optimize the primitive list:
*/
if (rmesa->vb.nrprims > 1) {
for (j = 0, i = 1 ; i < rmesa->vb.nrprims; i++) {
int pj = rmesa->vb.primlist[j].prim & 0xf;
int pi = rmesa->vb.primlist[i].prim & 0xf;
if (pj == pi && discreet_gl_prim[pj] &&
rmesa->vb.primlist[i].start == rmesa->vb.primlist[j].end) {
rmesa->vb.primlist[j].end = rmesa->vb.primlist[i].end;
}
else {
j++;
if (j != i) rmesa->vb.primlist[j] = rmesa->vb.primlist[i];
}
}
rmesa->vb.nrprims = j+1;
}
for (i = 0 ; i < rmesa->vb.nrprims; i++) {
if (RADEON_DEBUG & DEBUG_PRIMS)
fprintf(stderr, "vtxfmt prim %d: %s %d..%d\n", i,
_mesa_lookup_enum_by_nr( rmesa->vb.primlist[i].prim &
PRIM_MODE_MASK ),
rmesa->vb.primlist[i].start,
rmesa->vb.primlist[i].end);
radeonEmitPrimitive( rmesa->glCtx,
rmesa->vb.primlist[i].start,
rmesa->vb.primlist[i].end,
rmesa->vb.primlist[i].prim );
}
rmesa->vb.nrprims = 0;
radeonReleaseDmaRegion( rmesa, &tmp, __FUNCTION__ );
}
/* TCL render.
*/
static GLboolean radeon_run_tcl_render( struct gl_context *ctx,
struct tnl_pipeline_stage *stage )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
GLuint i;
/* TODO: separate this from the swtnl pipeline
*/
if (rmesa->radeon.TclFallback)
return GL_TRUE; /* fallback to software t&l */
if (VB->Count == 0)
return GL_FALSE;
/* NOTE: inputs != tnl->render_inputs - these are the untransformed
* inputs.
*/
if (ctx->Light.Enabled) {
inputs |= VERT_BIT_NORMAL;
}
if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
inputs |= VERT_BIT_COLOR1;
}
if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
inputs |= VERT_BIT_FOG;
}
for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
/* TODO: probably should not emit texture coords when texgen is enabled */
if (rmesa->TexGenNeedNormals[i]) {
inputs |= VERT_BIT_NORMAL;
}
inputs |= VERT_BIT_TEX(i);
}
}
radeonReleaseArrays( ctx, ~0 );
GLuint emit_end = radeonEnsureEmitSize( ctx, inputs )
+ rmesa->radeon.cmdbuf.cs->cdw;
radeonEmitArrays( ctx, inputs );
rmesa->tcl.Elts = VB->Elts;
for (i = 0 ; i < VB->PrimitiveCount ; i++)
{
GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
GLuint start = VB->Primitive[i].start;
GLuint length = VB->Primitive[i].count;
if (!length)
continue;
if (rmesa->tcl.Elts)
radeonEmitEltPrimitive( ctx, start, start+length, prim );
else
radeonEmitPrimitive( ctx, start, start+length, prim );
}
if (emit_end < rmesa->radeon.cmdbuf.cs->cdw)
WARN_ONCE("Rendering was %d commands larger than predicted size."
" We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end);
return GL_FALSE; /* finished the pipe */
}
/* TCL render.
*/
static GLboolean radeon_run_tcl_render( GLcontext *ctx,
struct tnl_pipeline_stage *stage )
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
GLuint i;
/* TODO: separate this from the swtnl pipeline
*/
if (rmesa->TclFallback)
return GL_TRUE; /* fallback to software t&l */
if (VB->Count == 0)
return GL_FALSE;
/* NOTE: inputs != tnl->render_inputs - these are the untransformed
* inputs.
*/
if (ctx->Light.Enabled) {
inputs |= VERT_BIT_NORMAL;
}
if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
inputs |= VERT_BIT_COLOR1;
}
if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
inputs |= VERT_BIT_FOG;
}
for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
/* TODO: probably should not emit texture coords when texgen is enabled */
if (rmesa->TexGenNeedNormals[i]) {
inputs |= VERT_BIT_NORMAL;
}
inputs |= VERT_BIT_TEX(i);
}
}
radeonReleaseArrays( ctx, ~0 );
radeonEmitArrays( ctx, inputs );
rmesa->tcl.Elts = VB->Elts;
for (i = 0 ; i < VB->PrimitiveCount ; i++)
{
GLuint prim = VB->Primitive[i].mode;
GLuint start = VB->Primitive[i].start;
GLuint length = VB->Primitive[i].count;
if (!length)
continue;
if (rmesa->tcl.Elts)
radeonEmitEltPrimitive( ctx, start, start+length, prim );
else
radeonEmitPrimitive( ctx, start, start+length, prim );
}
return GL_FALSE; /* finished the pipe */
}
