static void radeonClear( struct gl_context *ctx, GLbitfield mask )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
GLuint hwmask, swmask;
GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT |
BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
BUFFER_BIT_COLOR0;
if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
rmesa->radeon.front_buffer_dirty = GL_TRUE;
}
if ( RADEON_DEBUG & RADEON_IOCTL ) {
fprintf( stderr, "radeonClear\n");
}
radeon_firevertices(&rmesa->radeon);
hwmask = mask & hwbits;
swmask = mask & ~hwbits;
if ( swmask ) {
if (RADEON_DEBUG & RADEON_FALLBACKS)
fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask);
_swrast_Clear( ctx, swmask );
}
if ( !hwmask )
return;
radeonUserClear(ctx, hwmask);
}
static void radeonClear( struct gl_context *ctx, GLbitfield mask )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
GLuint flags = 0;
GLuint orig_mask = mask;
if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
rmesa->radeon.front_buffer_dirty = GL_TRUE;
}
if ( RADEON_DEBUG & RADEON_IOCTL ) {
fprintf( stderr, "radeonClear\n");
}
radeon_firevertices(&rmesa->radeon);
if ( mask & BUFFER_BIT_FRONT_LEFT ) {
flags |= RADEON_FRONT;
mask &= ~BUFFER_BIT_FRONT_LEFT;
}
if ( mask & BUFFER_BIT_BACK_LEFT ) {
flags |= RADEON_BACK;
mask &= ~BUFFER_BIT_BACK_LEFT;
}
if ( mask & BUFFER_BIT_DEPTH ) {
flags |= RADEON_DEPTH;
mask &= ~BUFFER_BIT_DEPTH;
}
if ( (mask & BUFFER_BIT_STENCIL) ) {
flags |= RADEON_STENCIL;
mask &= ~BUFFER_BIT_STENCIL;
}
if ( mask ) {
if (RADEON_DEBUG & RADEON_FALLBACKS)
fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
_swrast_Clear( ctx, mask );
}
if ( !flags )
return;
if (rmesa->using_hyperz) {
flags |= RADEON_USE_COMP_ZBUF;
/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
flags |= RADEON_USE_HIERZ; */
if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
flags |= RADEON_CLEAR_FASTZ;
}
}
radeonUserClear(ctx, orig_mask);
}
static void radeonClear( GLcontext *ctx, GLbitfield mask )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon);
GLuint flags = 0;
GLuint color_mask = 0;
GLuint orig_mask = mask;
if ( RADEON_DEBUG & RADEON_IOCTL ) {
fprintf( stderr, "radeonClear\n");
}
{
LOCK_HARDWARE( &rmesa->radeon );
UNLOCK_HARDWARE( &rmesa->radeon );
if ( dPriv->numClipRects == 0 )
return;
}
radeon_firevertices(&rmesa->radeon);
if ( mask & BUFFER_BIT_FRONT_LEFT ) {
flags |= RADEON_FRONT;
color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
mask &= ~BUFFER_BIT_FRONT_LEFT;
}
if ( mask & BUFFER_BIT_BACK_LEFT ) {
flags |= RADEON_BACK;
color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
mask &= ~BUFFER_BIT_BACK_LEFT;
}
if ( mask & BUFFER_BIT_DEPTH ) {
flags |= RADEON_DEPTH;
mask &= ~BUFFER_BIT_DEPTH;
}
if ( (mask & BUFFER_BIT_STENCIL) ) {
flags |= RADEON_STENCIL;
mask &= ~BUFFER_BIT_STENCIL;
}
if ( mask ) {
if (RADEON_DEBUG & RADEON_FALLBACKS)
fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
_swrast_Clear( ctx, mask );
}
if ( !flags )
return;
if (rmesa->using_hyperz) {
flags |= RADEON_USE_COMP_ZBUF;
/* if (rmesa->radeon.radeonScreen->chipset & RADEON_CHIPSET_TCL)
flags |= RADEON_USE_HIERZ; */
if (((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
((rmesa->radeon.state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) {
flags |= RADEON_CLEAR_FASTZ;
}
}
if (rmesa->radeon.radeonScreen->kernel_mm)
radeonUserClear(ctx, orig_mask);
else {
radeonKernelClear(ctx, flags);
rmesa->radeon.hw.all_dirty = GL_TRUE;
}
}
/* ================================================================
* Buffer clear
*/
static void r200Clear( struct gl_context *ctx, GLbitfield mask )
{
r200ContextPtr rmesa = R200_CONTEXT(ctx);
__DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon);
GLuint flags = 0;
GLuint orig_mask = mask;
if ( R200_DEBUG & RADEON_IOCTL ) {
if (rmesa->radeon.sarea)
fprintf( stderr, "r200Clear %x %d\n", mask, rmesa->radeon.sarea->pfCurrentPage);
else
fprintf( stderr, "r200Clear %x radeon->sarea is NULL\n", mask);
}
{
LOCK_HARDWARE( &rmesa->radeon );
UNLOCK_HARDWARE( &rmesa->radeon );
if ( dPriv->numClipRects == 0 )
return;
}
radeonFlush( ctx );
if ( mask & BUFFER_BIT_FRONT_LEFT ) {
flags |= RADEON_FRONT;
mask &= ~BUFFER_BIT_FRONT_LEFT;
}
if ( mask & BUFFER_BIT_BACK_LEFT ) {
flags |= RADEON_BACK;
mask &= ~BUFFER_BIT_BACK_LEFT;
}
if ( mask & BUFFER_BIT_DEPTH ) {
flags |= RADEON_DEPTH;
mask &= ~BUFFER_BIT_DEPTH;
}
if ( (mask & BUFFER_BIT_STENCIL) ) {
flags |= RADEON_STENCIL;
mask &= ~BUFFER_BIT_STENCIL;
}
if ( mask ) {
if (R200_DEBUG & RADEON_FALLBACKS)
fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
_swrast_Clear( ctx, mask );
}
if ( !flags )
return;
if (rmesa->using_hyperz) {
flags |= RADEON_USE_COMP_ZBUF;
/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200)
flags |= RADEON_USE_HIERZ; */
if (!((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) &&
((rmesa->radeon.state.stencil.clear & R200_STENCIL_WRITE_MASK) == R200_STENCIL_WRITE_MASK))) {
flags |= RADEON_CLEAR_FASTZ;
}
}
if (rmesa->radeon.radeonScreen->kernel_mm)
radeonUserClear(ctx, orig_mask);
else {
r200KernelClear(ctx, flags);
rmesa->radeon.hw.all_dirty = GL_TRUE;
}
}
