int radeon_asic_init(struct radeon_device *rdev) { radeon_register_accessor_init(rdev); switch (rdev->family) { case CHIP_R100: case CHIP_RV100: case CHIP_RS100: case CHIP_RV200: case CHIP_RS200: rdev->asic = &r100_asic; break; case CHIP_R200: case CHIP_RV250: case CHIP_RS300: case CHIP_RV280: rdev->asic = &r200_asic; break; case CHIP_R300: case CHIP_R350: case CHIP_RV350: case CHIP_RV380: if (rdev->flags & RADEON_IS_PCIE) rdev->asic = &r300_asic_pcie; else rdev->asic = &r300_asic; break; case CHIP_R420: case CHIP_R423: case CHIP_RV410: rdev->asic = &r420_asic; /* handle macs */ if (rdev->bios == NULL) { rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; rdev->asic->set_memory_clock = NULL; } break; case CHIP_RS400: case CHIP_RS480: rdev->asic = &rs400_asic; break; case CHIP_RS600: rdev->asic = &rs600_asic; break; case CHIP_RS690: case CHIP_RS740: rdev->asic = &rs690_asic; break; case CHIP_RV515: rdev->asic = &rv515_asic; break; case CHIP_R520: case CHIP_RV530: case CHIP_RV560: case CHIP_RV570: case CHIP_R580: rdev->asic = &r520_asic; break; case CHIP_R600: case CHIP_RV610: case CHIP_RV630: case CHIP_RV620: case CHIP_RV635: case CHIP_RV670: rdev->asic = &r600_asic; break; case CHIP_RS780: case CHIP_RS880: rdev->asic = &rs780_asic; break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: rdev->asic = &rv770_asic; break; case CHIP_CEDAR: case CHIP_REDWOOD: case CHIP_JUNIPER: case CHIP_CYPRESS: case CHIP_HEMLOCK: rdev->asic = &evergreen_asic; break; case CHIP_PALM: rdev->asic = &sumo_asic; break; case CHIP_BARTS: case CHIP_TURKS: case CHIP_CAICOS: rdev->asic = &btc_asic; break; default: /* FIXME: not supported yet */ return -EINVAL; } if (rdev->flags & RADEON_IS_IGP) { rdev->asic->get_memory_clock = NULL; rdev->asic->set_memory_clock = NULL; } /* set the number of crtcs */ if (rdev->flags & RADEON_SINGLE_CRTC) rdev->num_crtc = 1; else { if (ASIC_IS_DCE41(rdev)) rdev->num_crtc = 2; else if (ASIC_IS_DCE4(rdev)) rdev->num_crtc = 6; else rdev->num_crtc = 2; } return 0; }
int radeon_asic_init(struct radeon_device *rdev) { radeon_register_accessor_init(rdev); if (rdev->flags & RADEON_SINGLE_CRTC) rdev->num_crtc = 1; else rdev->num_crtc = 2; switch (rdev->family) { case CHIP_R100: case CHIP_RV100: case CHIP_RS100: case CHIP_RV200: case CHIP_RS200: rdev->asic = &r100_asic; break; case CHIP_R200: case CHIP_RV250: case CHIP_RS300: case CHIP_RV280: rdev->asic = &r200_asic; break; case CHIP_R300: case CHIP_R350: case CHIP_RV350: case CHIP_RV380: if (rdev->flags & RADEON_IS_PCIE) rdev->asic = &r300_asic_pcie; else rdev->asic = &r300_asic; break; case CHIP_R420: case CHIP_R423: case CHIP_RV410: rdev->asic = &r420_asic; if (rdev->bios == NULL) { rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; rdev->asic->pm.set_memory_clock = NULL; } break; case CHIP_RS400: case CHIP_RS480: rdev->asic = &rs400_asic; break; case CHIP_RS600: rdev->asic = &rs600_asic; break; case CHIP_RS690: case CHIP_RS740: rdev->asic = &rs690_asic; break; case CHIP_RV515: rdev->asic = &rv515_asic; break; case CHIP_R520: case CHIP_RV530: case CHIP_RV560: case CHIP_RV570: case CHIP_R580: rdev->asic = &r520_asic; break; case CHIP_R600: case CHIP_RV610: case CHIP_RV630: case CHIP_RV620: case CHIP_RV635: case CHIP_RV670: rdev->asic = &r600_asic; break; case CHIP_RS780: case CHIP_RS880: rdev->asic = &rs780_asic; break; case CHIP_RV770: case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: rdev->asic = &rv770_asic; break; case CHIP_CEDAR: case CHIP_REDWOOD: case CHIP_JUNIPER: case CHIP_CYPRESS: case CHIP_HEMLOCK: if (rdev->family == CHIP_CEDAR) rdev->num_crtc = 4; else rdev->num_crtc = 6; rdev->asic = &evergreen_asic; break; case CHIP_PALM: case CHIP_SUMO: case CHIP_SUMO2: rdev->asic = &sumo_asic; break; case CHIP_BARTS: case CHIP_TURKS: case CHIP_CAICOS: if (rdev->family == CHIP_CAICOS) rdev->num_crtc = 4; else rdev->num_crtc = 6; rdev->asic = &btc_asic; break; case CHIP_CAYMAN: rdev->asic = &cayman_asic; rdev->num_crtc = 6; rdev->vm_manager.funcs = &cayman_vm_funcs; break; case CHIP_ARUBA: rdev->asic = &trinity_asic; rdev->num_crtc = 4; rdev->vm_manager.funcs = &cayman_vm_funcs; break; case CHIP_TAHITI: case CHIP_PITCAIRN: case CHIP_VERDE: rdev->asic = &si_asic; rdev->num_crtc = 6; rdev->vm_manager.funcs = &si_vm_funcs; break; default: return -EINVAL; } if (rdev->flags & RADEON_IS_IGP) { rdev->asic->pm.get_memory_clock = NULL; rdev->asic->pm.set_memory_clock = NULL; } return 0; }