static void pm_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { pci_default_write_config(d, address, val, len); if (range_covers_byte(address, len, 0x80) || ranges_overlap(address, len, 0x40, 4)) { pm_io_space_update((PIIX4PMState *)d); } if (range_covers_byte(address, len, 0xd2) || ranges_overlap(address, len, 0x90, 4)) { smbus_io_space_update((PIIX4PMState *)d); } }
static void pm_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { pci_default_write_config(d, address, val, len); if (range_covers_byte(address, len, 0x80)) pm_io_space_update((PIIX4PMState *)d); }
/* Handle MSI-X capability config write. */ void msix_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len) { unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET; int vector; bool was_masked; if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) { return; } was_masked = dev->msix_function_masked; msix_update_function_masked(dev); if (!msix_enabled(dev)) { return; } pci_device_deassert_intx(dev); if (dev->msix_function_masked == was_masked) { return; } for (vector = 0; vector < dev->msix_entries_nr; ++vector) { msix_handle_mask_update(dev, vector, msix_vector_masked(dev, vector, was_masked)); } }
/** * Map guest physical address to host pointer */ void *hostmem_lookup(HostMem *hostmem, uint64_t phys, uint64_t len, bool is_write) { struct vhost_memory_region *found = NULL; void *host_addr = NULL; uint64_t offset_within_region; unsigned int i; is_write = is_write; /*r/w information is currently not tracked */ qemu_mutex_lock(&hostmem->mem_lock); for (i = 0; i < hostmem->mem->nregions; i++) { struct vhost_memory_region *region = &hostmem->mem->regions[i]; if (range_covers_byte(region->guest_phys_addr, region->memory_size, phys)) { found = region; break; } } if (!found) { goto out; } offset_within_region = phys - found->guest_phys_addr; if (len <= found->memory_size - offset_within_region) { host_addr = (void*)(uintptr_t)(found->userspace_addr + offset_within_region); } out: qemu_mutex_unlock(&hostmem->mem_lock); return host_addr; }
static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, uint32_t val, int len) { E1000EState *s = E1000E(pci_dev); pci_default_write_config(pci_dev, address, val, len); if (range_covers_byte(address, len, PCI_COMMAND) && (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { e1000e_start_recv(&s->core); } }
static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address, uint32_t val, int len) { E1000EState *s = E1000E(pci_dev); pci_default_write_config(pci_dev, address, val, len); if (range_covers_byte(address, len, PCI_COMMAND) && (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } }
static void usb_ehci_pci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int l) { EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev); bool busmaster; pci_default_write_config(dev, addr, val, l); if (!range_covers_byte(addr, l, PCI_COMMAND)) { return; } busmaster = pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_MASTER; i->ehci.dma = busmaster ? pci_dma_context(dev) : NULL; }