void cc1101_t::Init() { // ==== GPIO ==== PinSetupOut (GPIOA, CC_CS, omPushPull, pudNone); PinSetupAlterFunc(GPIOA, CC_SCK, omPushPull, pudNone, AF5); PinSetupAlterFunc(GPIOA, CC_MISO, omPushPull, pudNone, AF5); PinSetupAlterFunc(GPIOA, CC_MOSI, omPushPull, pudNone, AF5); PinSetupIn (GPIOA, CC_GDO0, pudNone); PinSetupIn (GPIOA, CC_GDO2, pudNone); CsHi(); // ==== SPI ==== MSB first, master, SCK idle low, Baudrate=f/2 rccEnableSPI1(FALSE); // NoCRC, FullDuplex, 8bit, MSB, Baudrate, Master, ClkLowIdle(CPOL=0), // FirstEdge(CPHA=0), NSS software controlled and is 1 CC_SPI->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR; CC_SPI->CR2 = 0; CC_SPI->I2SCFGR &= ~((uint16_t)SPI_I2SCFGR_I2SMOD); CC_SPI->CR1 |= SPI_CR1_SPE; // Enable SPI // ==== Init CC ==== CReset(); FlushRxFIFO(); RfConfig(); // ==== IRQ ==== rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE); // Enable sys cfg controller SYSCFG->EXTICR[1] &= 0xFFFFFFF0; // EXTI4 is connected to PortA // Configure EXTI line EXTI->IMR |= GPIO0_IRQ_MASK; // Interrupt mode enabled EXTI->EMR &= ~GPIO0_IRQ_MASK; // Event mode disabled EXTI->RTSR &= ~GPIO0_IRQ_MASK; // Rising trigger disabled EXTI->FTSR |= GPIO0_IRQ_MASK; // Falling trigger enabled EXTI->PR = GPIO0_IRQ_MASK; // Clean irq flag nvicEnableVector(EXTI4_IRQn, CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); }
/** * @brief Configures and activates the SPI peripheral. * * @param[in] spip pointer to the @p SPIDriver object * * @notapi */ void spi_lld_start(SPIDriver *spip) { uint32_t ds; /* If in stopped state then enables the SPI and DMA clocks.*/ if (spip->state == SPI_STOP) { #if STM32_SPI_USE_SPI1 if (&SPID1 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); rccEnableSPI1(FALSE); } #endif #if STM32_SPI_USE_SPI2 if (&SPID2 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); rccEnableSPI2(FALSE); } #endif #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); rccEnableSPI3(FALSE); } #endif /* DMA setup.*/ dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); } /* Configuration-specific DMA setup.*/ ds = spip->config->cr2 & SPI_CR2_DS; if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) { /* Frame width is 8 bits or smaller.*/ spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; } else { /* Frame width is larger than 8 bits.*/ spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; } /* SPI setup and enable.*/ spip->spi->CR1 = 0; spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | SPI_CR1_SSI; spip->spi->CR2 = spip->config->cr2 | SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; spip->spi->CR1 |= SPI_CR1_SPE; }
/** * @brief Configures and activates the SPI peripheral. * * @param[in] spip pointer to the @p SPIDriver object * * @notapi */ void spi_lld_start(SPIDriver *spip) { /* If in stopped state then enables the SPI and DMA clocks.*/ if (spip->state == SPI_STOP) { #if STM32_SPI_USE_SPI1 if (&SPID1 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); rccEnableSPI1(FALSE); } #endif #if STM32_SPI_USE_SPI2 if (&SPID2 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); rccEnableSPI2(FALSE); } #endif #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); rccEnableSPI3(FALSE); } #endif #if STM32_SPI_USE_SPI4 if (&SPID4 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI4_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #7", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI4_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #8", "stream already allocated"); rccEnableSPI4(FALSE); } #endif #if STM32_SPI_USE_SPI5 if (&SPID5 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI5_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #9", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI5_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #10", "stream already allocated"); rccEnableSPI5(FALSE); } #endif #if STM32_SPI_USE_SPI6 if (&SPID6 == spip) { bool_t b; b = dmaStreamAllocate(spip->dmarx, STM32_SPI_SPI6_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #11", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI6_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); chDbgAssert(!b, "spi_lld_start(), #12", "stream already allocated"); rccEnableSPI6(FALSE); } #endif /* DMA setup.*/ dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR); dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR); } /* Configuration-specific DMA setup.*/ if ((spip->config->cr1 & SPI_CR1_DFF) == 0) { /* Frame width is 8 bits or smaller.*/ spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; } else { /* Frame width is larger than 8 bits.*/ spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; } /* SPI setup and enable.*/ #if !defined(STM32_SPI_SLAVE_MODE) spip->spi->CR1 = 0; spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | SPI_CR1_SSI; spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; spip->spi->CR1 |= SPI_CR1_SPE; #else spip->spi->CR1 = spip->config->cr1| SPI_CR1_LSBFIRST| SPI_CR1_DFF;// | SPI_CR1_RXONLY; //| SPI_CR1_DFF; spip->spi->CR2 = SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; //| SPI_CR2_RXNEIE; spip->spi->CR1 |= SPI_CR1_SPE; #endif }