void Enc28j60::reset(void)
{
// Trigger a software reset
writeOperation(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
// Errata #2: Wait for at least 1 ms after software reset
for (uint32_t i = 0x1FFF; i != 0; i--)
;
// Wait until the clock becomes ready
while(!readOperation(ENC28J60_READ_CTRL_REG, ESTAT) & ESTAT_CLKRDY);
// Store a pointer to the next packet
nextPacketPtr = RXSTART_INIT;
// Set the packet transmit and receive buffers
writeRegister(ERXST, RXSTART_INIT);
writeRegister(ERXRDPT, RXSTART_INIT);
writeRegister(ERXND, RXSTOP_INIT);
writeRegister(ETXST, TXSTART_INIT);
writeRegister(ETXND, TXSTOP_INIT);
// Set MACON1 register
writeRegisterByte(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
// Set MACON2 register
writeRegisterByte(MACON2, 0x00);
// Set MACON3 registers
writeOperation(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);
// Set Non-Back-to-Back Inter-Packet Gap
writeRegister(MAIPG, 0x0C12);
// Set Back-to-Back Inter-Packet Gap
writeRegisterByte(MABBIPG, 0x12);
// Set maximum frame length
writeRegister(MAMXFL, MAX_FRAMELEN);
// Set MAC address
writeRegisterByte(MAADR5, macAddress[0]);
writeRegisterByte(MAADR4, macAddress[1]);
writeRegisterByte(MAADR3, macAddress[2]);
writeRegisterByte(MAADR2, macAddress[3]);
writeRegisterByte(MAADR1, macAddress[4]);
writeRegisterByte(MAADR0, macAddress[5]);
// Errata #9/10: Disable loopback in half-duplex
writePhy(PHCON2, PHCON2_HDLDIS);
// Set ECON1 bank
setBank(ECON1);
// Enable packet interrupt
writeOperation(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE | EIE_PKTIE);
// Enable packet reception
writeOperation(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
}
OperationResult Enc28j60::transmitFrame(uint8_t* data, uint32_t length)
{
// Errata #12: In half-duplex, transmit logic may stall
while (readOperation(ENC28J60_READ_CTRL_REG, ECON1) & ECON1_TXRTS)
{
if (readRegisterByte(EIR) & EIR_TXERIF)
{
writeOperation(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
writeOperation(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
}
}
// Set transmit buffer start and end
writeRegister(EWRPT, TXSTART_INIT);
writeRegister(ETXND, TXSTART_INIT + length);
// Use default per packet control bytes
writeOperation(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
// Write data to buffer
writeBuffer(data, length);
// Enable transmission
writeOperation(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
return ResultSuccess;
}
Instruction encodeInst(std::string const& dis_)
{
Instruction inst;
std::string dis;
bool not_num = true;
for(char s : dis_){
if(!not_num){
dis += s;
}else if(::isalpha(s)){
dis += static_cast<char>(::toupper(s));
}else if(::isdigit(s)){
not_num = false;
dis += s;
}else if(!::isspace(s)){
dis += s;
}
}
if(readOperation(inst, dis) < 0) {
inst.op_ = Operation::Invalid;
}else if(readAddrMode(inst, dis.substr(3)) < 0){
inst.op_ = Operation::Invalid;
}
if(inst.op_ != Operation::Invalid){
unsigned int code = static_cast<unsigned int>(inst.op_) | static_cast<unsigned int>(inst.addrMode_);
for(int i=0;i<256;++i){
if( symCode[i] == code ) {
inst.bin[0] = i;
return inst;
}
}
}
inst.op_ = Operation::Invalid;
return inst;
}
