static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
{
int i;
u16 out, select;
u8 bit;
u32 bangdata = (data << 4) | (adr & 0xf);
out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
write_nic_word(dev, RFPinsEnable,
(read_nic_word(dev, RFPinsEnable) | 0x7));
select = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsSelect, select | 0x7 |
SW_CONTROL_GPIO);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(2);
write_nic_word(dev, RFPinsOutput, out);
force_pci_posting(dev);
udelay(10);
for (i = 15; i >= 0; i--) {
bit = (bangdata & (1 << i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
i--;
bit = (bangdata & (1 << i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out);
}
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
write_nic_word(dev, RFPinsSelect, select | SW_CONTROL_GPIO);
rtl8185_rf_pins_enable(dev);
}
bool FirmwareEnableCPU(struct net_device *dev)
{
bool rtStatus = true;
u8 tmpU1b, CPUStatus = 0;
u16 tmpU2b;
u32 iCheckTime = 200;
/* Enable CPU. */
tmpU1b = read_nic_byte(dev, SYS_CLKR);
/* AFE source */
write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL));
tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN));
/* Poll IMEM Ready after CPU has refilled. */
do {
CPUStatus = read_nic_byte(dev, TCR);
if (CPUStatus & IMEM_RDY)
/* success */
break;
udelay(100);
} while (iCheckTime--);
if (!(CPUStatus & IMEM_RDY)) {
RT_TRACE(COMP_ERR, "%s(): failed to enable CPU", __func__);
rtStatus = false;
}
return rtStatus;
}
static void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
{
write_nic_word(dev, offset, data);
/*
* To make sure write operation is completed,
* 2005.11.09, by rcnjko.
*/
read_nic_word(dev, offset);
}
RT_STATUS
FirmwareEnableCPU(struct net_device *dev)
{
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
u8 tmpU1b, CPUStatus = 0;
u16 tmpU2b;
u32 iCheckTime = 200;
RT_TRACE(COMP_FIRMWARE, "-->FirmwareEnableCPU()\n" );
// Enable CPU.
tmpU1b = read_nic_byte(dev, SYS_CLKR);
write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL)); //AFE source
tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN));
//Polling IMEM Ready after CPU has refilled.
do
{
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& IMEM_RDY)
{
RT_TRACE(COMP_FIRMWARE, "IMEM Ready after CPU has refilled.\n");
break;
}
//usleep(100);
udelay(100);
}while(iCheckTime--);
if(!(CPUStatus & IMEM_RDY))
return RT_STATUS_FAILURE;
RT_TRACE(COMP_FIRMWARE, "<--FirmwareEnableCPU(): rtStatus(%#x)\n", rtStatus);
return rtStatus;
}
bool
FirmwareEnableCPU(struct net_device *dev)
{
bool rtStatus = true;
u8 tmpU1b, CPUStatus = 0;
u16 tmpU2b;
u32 iCheckTime = 200;
RT_TRACE(COMP_FIRMWARE, "-->FirmwareEnableCPU()\n" );
fw_SetRQPN(dev);
tmpU1b = read_nic_byte(dev, SYS_CLKR);
write_nic_byte(dev, SYS_CLKR, (tmpU1b|SYS_CPU_CLKSEL));
tmpU2b = read_nic_word(dev, SYS_FUNC_EN);
write_nic_word(dev, SYS_FUNC_EN, (tmpU2b|FEN_CPUEN));
do
{
CPUStatus = read_nic_byte(dev, TCR);
if(CPUStatus& IMEM_RDY)
{
RT_TRACE(COMP_FIRMWARE, "IMEM Ready after CPU has refilled.\n");
break;
}
udelay(100);
}while(iCheckTime--);
if(!(CPUStatus & IMEM_RDY))
return false;
RT_TRACE(COMP_FIRMWARE, "<--FirmwareEnableCPU(): rtStatus(%#x)\n", rtStatus);
return rtStatus;
}
void rtl8225_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
priv->chan = channel;
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
if(priv->card_type == USB)
rtl8225_host_usb_init(dev);
else
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
#if 0
if(priv->card_8185 == 1){/* version C or B */
if(priv->card_8185_Bversion) /* version B*/
write_nic_dword(dev, RF_PARA, 0x44);
else /* version C */
write_nic_dword(dev, RF_PARA, 0x100044);
}else{ /* version D */
if(priv->enable_gpio0)
write_nic_dword(dev, RF_PARA, 0x20100044);
else /* also USB */
write_nic_dword(dev, RF_PARA, 0x100044);
}
#endif
write_nic_dword(dev, RF_PARA, 0x100044);
#if 1 //0->1
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
#endif
if(priv->card_type == USB){
rtl8185_rf_pins_enable(dev);
mdelay(1000);
}
write_rtl8225(dev, 0x0, 0x67); mdelay(1);
write_rtl8225(dev, 0x1, 0xfe0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
if(priv->card_type == USB)
write_rtl8225(dev, 0x4, 0x486);
else
write_rtl8225(dev, 0x4, 0x8be);
mdelay(1);
#if 0
}else if(priv->phy_ver == 1){
void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
{
int i;
u16 out,select;
u8 bit;
u32 bangdata = (data << 4) | (adr & 0xf);
struct r8180_priv *priv = ieee80211_priv(dev);
out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
write_nic_word(dev,RFPinsEnable,
(read_nic_word(dev,RFPinsEnable) | 0x7));
select = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsSelect, select | 0x7 |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN );//| 0x1fff);
force_pci_posting(dev);
udelay(2);
write_nic_word(dev, RFPinsOutput, out);
force_pci_posting(dev);
udelay(10);
for(i=15; i>=0;i--){
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
i--;
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out);
}
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out |
((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
write_nic_word(dev, RFPinsSelect, select |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
if(priv->card_type == USB)
mdelay(2);
else
rtl8185_rf_pins_enable(dev);
}
bool FirmwareDownload92S(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rtStatus = true;
const char *pFwImageFileName[1] = {"RTL8192SU/rtl8192sfw.bin"};
u8 *pucMappedFile = NULL;
u32 ulFileLength, ulInitStep = 0;
u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE;
rt_firmware *pFirmware = priv->pFirmware;
u8 FwStatus = FW_STATUS_INIT;
PRT_8192S_FIRMWARE_HDR pFwHdr = NULL;
PRT_8192S_FIRMWARE_PRIV pFwPriv = NULL;
int rc;
const struct firmware *fw_entry;
u32 file_length = 0;
pFirmware->FWStatus = FW_STATUS_INIT;
RT_TRACE(COMP_FIRMWARE, " --->FirmwareDownload92S()\n");
//3//
//3 //<1> Open Image file, and map file to contineous memory if open file success.
//3 // or read image file from array. Default load from BIN file
//3//
priv->firmware_source = FW_SOURCE_IMG_FILE;// We should decided by Reg.
switch( priv->firmware_source )
{
case FW_SOURCE_IMG_FILE:
if(pFirmware->szFwTmpBufferLen == 0)
{
rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->udev->dev);//===>1
if(rc < 0 ) {
RT_TRACE(COMP_ERR, "request firmware fail!\n");
goto DownloadFirmware_Fail;
}
if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer))
{
RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
release_firmware(fw_entry);
goto DownloadFirmware_Fail;
}
memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size);
pFirmware->szFwTmpBufferLen = fw_entry->size;
release_firmware(fw_entry);
pucMappedFile = pFirmware->szFwTmpBuffer;
file_length = pFirmware->szFwTmpBufferLen;
//Retrieve FW header.
pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
pFwHdr = pFirmware->pFwHeader;
RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
{
RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\
__FUNCTION__);
goto DownloadFirmware_Fail;
} else {
pucMappedFile+=FwHdrSize;
//Retrieve IMEM image.
memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
}
if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
{
RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\
__FUNCTION__);
goto DownloadFirmware_Fail;
} else {
pucMappedFile += pFirmware->FwIMEMLen;
/* Retriecve EMEM image */
memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);//===>6
pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
}
}
break;
case FW_SOURCE_HEADER_FILE:
#if 1
#define Rtl819XFwImageArray Rtl8192SUFwImgArray
//2008.11.10 Add by tynli.
pucMappedFile = Rtl819XFwImageArray;
ulFileLength = ImgArrayLength;
RT_TRACE(COMP_INIT,"Fw download from header.\n");
/* Retrieve FW header*/
pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
pFwHdr = pFirmware->pFwHeader;
RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
{
printk("FirmwareDownload92S(): memory for data image is less than IMEM required\n");
goto DownloadFirmware_Fail;
} else {
pucMappedFile+=FwHdrSize;
//Retrieve IMEM image.
memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
}
if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
{
printk(" FirmwareDownload92S(): memory for data image is less than EMEM required\n");
goto DownloadFirmware_Fail;
} else {
pucMappedFile+= pFirmware->FwIMEMLen;
//Retriecve EMEM image.
memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
}
#endif
break;
default:
break;
}
FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
while(FwStatus!= FW_STATUS_READY)
{
// Image buffer redirection.
switch(FwStatus)
{
case FW_STATUS_LOAD_IMEM:
pucMappedFile = pFirmware->FwIMEM;
ulFileLength = pFirmware->FwIMEMLen;
break;
case FW_STATUS_LOAD_EMEM:
pucMappedFile = pFirmware->FwEMEM;
ulFileLength = pFirmware->FwEMEMLen;
break;
case FW_STATUS_LOAD_DMEM:
/* <Roger_Notes> Partial update the content of header private. 2008.12.18 */
pFwHdr = pFirmware->pFwHeader;
pFwPriv = (PRT_8192S_FIRMWARE_PRIV)&pFwHdr->FWPriv;
FirmwareHeaderPriveUpdate(dev, pFwPriv);
pucMappedFile = (u8*)(pFirmware->pFwHeader)+RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
ulFileLength = FwHdrSize-RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
break;
default:
RT_TRACE(COMP_ERR, "Unexpected Download step!!\n");
goto DownloadFirmware_Fail;
break;
}
//3//
//3// <2> Download image file
//3 //
rtStatus = FirmwareDownloadCode(dev, pucMappedFile, ulFileLength);
if(rtStatus != true)
{
RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n" );
goto DownloadFirmware_Fail;
}
//3//
//3// <3> Check whether load FW process is ready
//3 //
rtStatus = FirmwareCheckReady(dev, FwStatus);
if(rtStatus != true)
{
RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n");
goto DownloadFirmware_Fail;
}
FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
}
RT_TRACE(COMP_FIRMWARE, "Firmware Download Success!!\n");
return rtStatus;
DownloadFirmware_Fail:
RT_TRACE(COMP_ERR, "Firmware Download Fail!!%x\n",read_nic_word(dev, TCR));
rtStatus = false;
return rtStatus;
}
bool FirmwareDownload92S(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true;
u8 *pucMappedFile = NULL;
u32 ulFileLength = 0;
u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE;
rt_firmware *pFirmware = priv->pFirmware;
u8 FwStatus = FW_STATUS_INIT;
PRT_8192S_FIRMWARE_HDR pFwHdr = NULL;
PRT_8192S_FIRMWARE_PRIV pFwPriv = NULL;
pFirmware->FWStatus = FW_STATUS_INIT;
RT_TRACE(COMP_FIRMWARE, " --->FirmwareDownload92S()\n");
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) && defined(USE_FW_SOURCE_IMG_FILE)
priv->firmware_source = FW_SOURCE_IMG_FILE;
#else
priv->firmware_source = FW_SOURCE_HEADER_FILE;
#endif
switch( priv->firmware_source )
{
case FW_SOURCE_IMG_FILE:
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) && defined(USE_FW_SOURCE_IMG_FILE)
if(pFirmware->szFwTmpBufferLen == 0)
{
#ifdef _RTL8192_EXT_PATCH_
const char *pFwImageFileName[1] = {"RTL8191SE_MESH/rtl8192sfw.bin"};
#else
const char *pFwImageFileName[1] = {"RTL8192SE/rtl8192sfw.bin"};
#endif
const struct firmware *fw_entry = NULL;
u32 ulInitStep = 0;
int rc = 0;
u32 file_length = 0;
rc = request_firmware(&fw_entry, pFwImageFileName[ulInitStep],&priv->pdev->dev);
if(rc < 0 ) {
RT_TRACE(COMP_ERR, "request firmware fail!\n");
goto DownloadFirmware_Fail;
}
if(fw_entry->size > sizeof(pFirmware->szFwTmpBuffer)) {
RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n");
release_firmware(fw_entry);
goto DownloadFirmware_Fail;
}
memcpy(pFirmware->szFwTmpBuffer,fw_entry->data,fw_entry->size);
pFirmware->szFwTmpBufferLen = fw_entry->size;
release_firmware(fw_entry);
pucMappedFile = pFirmware->szFwTmpBuffer;
file_length = pFirmware->szFwTmpBufferLen;
pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
pFwHdr = pFirmware->pFwHeader;
RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
{
RT_TRACE(COMP_ERR, "%s: memory for data image is less than IMEM required\n",\
__FUNCTION__);
goto DownloadFirmware_Fail;
} else {
pucMappedFile+=FwHdrSize;
memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
}
if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
{
RT_TRACE(COMP_ERR, "%s: memory for data image is less than EMEM required\n",\
__FUNCTION__);
goto DownloadFirmware_Fail;
}
else
{
pucMappedFile += pFirmware->FwIMEMLen;
memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
}
}
#endif
break;
case FW_SOURCE_HEADER_FILE:
#if 1
#define Rtl819XFwImageArray Rtl8192SEFwImgArray
pucMappedFile = Rtl819XFwImageArray;
ulFileLength = ImgArrayLength;
RT_TRACE(COMP_INIT,"Fw download from header.\n");
pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
pFwHdr = pFirmware->pFwHeader;
RT_TRACE(COMP_FIRMWARE,"signature:%x, version:%x, size:%x, imemsize:%x, sram size:%x\n", \
pFwHdr->Signature, pFwHdr->Version, pFwHdr->DMEMSize, \
pFwHdr->IMG_IMEM_SIZE, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FirmwareVersion = byte(pFwHdr->Version ,0);
if ((pFwHdr->IMG_IMEM_SIZE==0) || (pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM)))
{
printk("FirmwareDownload92S(): memory for data image is less than IMEM required\n");
goto DownloadFirmware_Fail;
}
else
{
pucMappedFile+=FwHdrSize;
memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
}
if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM))
{
printk(" FirmwareDownload92S(): memory for data image is less than EMEM required\n");
goto DownloadFirmware_Fail;
} else {
pucMappedFile+= pFirmware->FwIMEMLen;
memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
}
#endif
break;
default:
break;
}
FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
while(FwStatus!= FW_STATUS_READY)
{
switch(FwStatus)
{
case FW_STATUS_LOAD_IMEM:
pucMappedFile = pFirmware->FwIMEM;
ulFileLength = pFirmware->FwIMEMLen;
break;
case FW_STATUS_LOAD_EMEM:
pucMappedFile = pFirmware->FwEMEM;
ulFileLength = pFirmware->FwEMEMLen;
break;
case FW_STATUS_LOAD_DMEM:
pFwHdr = pFirmware->pFwHeader;
pFwPriv = (PRT_8192S_FIRMWARE_PRIV)&pFwHdr->FWPriv;
FirmwareHeaderPriveUpdate(dev, pFwPriv);
pucMappedFile = (u8*)(pFirmware->pFwHeader)+RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
ulFileLength = FwHdrSize-RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
break;
default:
RT_TRACE(COMP_ERR, "Unexpected Download step!!\n");
goto DownloadFirmware_Fail;
break;
}
rtStatus = FirmwareDownloadCode(dev, pucMappedFile, ulFileLength);
if(rtStatus != true)
{
RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n" );
goto DownloadFirmware_Fail;
}
rtStatus = FirmwareCheckReady(dev, FwStatus);
if(rtStatus != true)
{
RT_TRACE(COMP_ERR, "FirmwareDownloadCode() fail ! \n");
goto DownloadFirmware_Fail;
}
FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
}
RT_TRACE(COMP_FIRMWARE, "Firmware Download Success!!\n");
return rtStatus;
DownloadFirmware_Fail:
RT_TRACE(COMP_ERR, "Firmware Download Fail!!%x\n",read_nic_word(dev, TCR));
rtStatus = false;
return rtStatus;
}
void rtl8225z2_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
u32 data, addr;
priv->chan = channel;
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
write_nic_dword(dev, RF_PARA, 0x100044);
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
rtl8185_rf_pins_enable(dev);
write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
write_rtl8225(dev, 0x7, rtl8225_chan[channel]); mdelay(1);
write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
write_rtl8225(dev, 0x9, 0x335); mdelay(1);
write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
write_rtl8225(dev, 0xc, 0x850); mdelay(1);
write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
write_rtl8225(dev, 0xf, 0x114);
mdelay(100);
write_rtl8225(dev, 0x0, 0x1b7);
for (i = 0; i < 95; i++) {
write_rtl8225(dev, 0x1, (u8)(i + 1));
write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
}
write_rtl8225(dev, 0x3, 0x80);
write_rtl8225(dev, 0x5, 0x4);
write_rtl8225(dev, 0x0, 0xb7);
write_rtl8225(dev, 0x2, 0xc4d);
/* FIXME!! rtl8187 we have to check if calibrarion
* is successful and eventually cal. again (repeat
* the two write on reg 2)
*/
data = read_rtl8225(dev, 6);
if (!(data & 0x00000080)) {
write_rtl8225(dev, 0x02, 0x0c4d);
force_pci_posting(dev); mdelay(200);
write_rtl8225(dev, 0x02, 0x044d);
force_pci_posting(dev); mdelay(100);
data = read_rtl8225(dev, 6);
if (!(data & 0x00000080))
DMESGW("RF Calibration Failed!!!!\n");
}
mdelay(200);
write_rtl8225(dev, 0x0, 0x2bf);
for (i = 0; i < 128; i++) {
data = rtl8225_agc[i];
addr = i + 0x80; /* enable writing AGC table */
write_phy_ofdm(dev, 0xb, data);
mdelay(1);
write_phy_ofdm(dev, 0xa, addr);
mdelay(1);
}
force_pci_posting(dev);
mdelay(1);
write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
write_phy_ofdm(dev, 0x0d, 0x43);
write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
rtl8225z2_set_gain(dev, 4);
write_phy_cck(dev, 0x0, 0x98); mdelay(1);
write_phy_cck(dev, 0x3, 0x20); mdelay(1);
write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
write_phy_cck(dev, 0x5, 0x12); mdelay(1);
write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
write_phy_cck(dev, 0x7, 0x78); mdelay(1);
write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
write_phy_cck(dev, 0x10, 0x93); mdelay(1);
write_phy_cck(dev, 0x11, 0x88); mdelay(1);
write_phy_cck(dev, 0x12, 0x47); mdelay(1);
write_phy_cck(dev, 0x13, 0xd0);
write_phy_cck(dev, 0x19, 0x00);
write_phy_cck(dev, 0x1a, 0xa0);
write_phy_cck(dev, 0x1b, 0x08);
write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
write_phy_cck(dev, 0x42, 0x15); mdelay(1);
write_phy_cck(dev, 0x43, 0x18); mdelay(1);
write_phy_cck(dev, 0x44, 0x36); mdelay(1);
write_phy_cck(dev, 0x45, 0x35); mdelay(1);
write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
write_phy_cck(dev, 0x47, 0x25); mdelay(1);
write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
write_phy_cck(dev, 0x49, 0x12); mdelay(1);
write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
rtl8225z2_SetTXPowerLevel(dev, channel);
/* RX antenna default to A */
write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* B: 0xDB */
write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* B: 0x10 */
rtl8185_tx_antenna(dev, 0x03); /* B: 0x00 */
/* switch to high-speed 3-wire
* last digit. 2 for both cck and ofdm
*/
write_nic_dword(dev, 0x94, 0x15c00002);
rtl8185_rf_pins_enable(dev);
rtl8225_rf_set_chan(dev, priv->chan);
}
static u32 read_rtl8225(struct net_device *dev, u8 adr)
{
u32 data2Write = ((u32)(adr & 0x1f)) << 27;
u32 dataRead;
u32 mask;
u16 oval, oval2, oval3, tmp;
int i;
short bit, rw;
u8 wLength = 6;
u8 rLength = 12;
u8 low2high = 0;
oval = read_nic_word(dev, RFPinsOutput);
oval2 = read_nic_word(dev, RFPinsEnable);
oval3 = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsEnable, (oval2|0xf));
write_nic_word(dev, RFPinsSelect, (oval3|0xf));
dataRead = 0;
oval &= ~0xf;
write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN);
udelay(4);
write_nic_word(dev, RFPinsOutput, oval);
udelay(5);
rw = 0;
mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
for (i = 0; i < wLength/2; i++) {
bit = ((data2Write&mask) != 0) ? 1 : 0;
write_nic_word(dev, RFPinsOutput, bit | oval | rw);
udelay(1);
write_nic_word(dev, RFPinsOutput,
bit | oval | BB_HOST_BANG_CLK | rw);
udelay(2);
write_nic_word(dev, RFPinsOutput,
bit | oval | BB_HOST_BANG_CLK | rw);
udelay(2);
mask = (low2high) ? (mask<<1) : (mask>>1);
if (i == 2) {
rw = BB_HOST_BANG_RW;
write_nic_word(dev, RFPinsOutput,
bit | oval | BB_HOST_BANG_CLK | rw);
udelay(2);
write_nic_word(dev, RFPinsOutput, bit | oval | rw);
udelay(2);
break;
}
bit = ((data2Write&mask) != 0) ? 1 : 0;
write_nic_word(dev, RFPinsOutput,
oval | bit | rw | BB_HOST_BANG_CLK);
udelay(2);
write_nic_word(dev, RFPinsOutput,
oval | bit | rw | BB_HOST_BANG_CLK);
udelay(2);
write_nic_word(dev, RFPinsOutput, oval | bit | rw);
udelay(1);
mask = (low2high) ? (mask<<1) : (mask>>1);
}
write_nic_word(dev, RFPinsOutput, rw|oval);
udelay(2);
mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
/*
* We must set data pin to HW controlled, otherwise RF can't driver it
* and value RF register won't be able to read back properly.
*/
write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
for (i = 0; i < rLength; i++) {
write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
udelay(2);
write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
udelay(2);
write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
udelay(2);
tmp = read_nic_word(dev, RFPinsInput);
dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
mask = (low2high) ? (mask<<1) : (mask>>1);
}
write_nic_word(dev, RFPinsOutput,
BB_HOST_BANG_EN | BB_HOST_BANG_RW | oval);
udelay(2);
write_nic_word(dev, RFPinsEnable, oval2);
write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
write_nic_word(dev, RFPinsOutput, 0x3a0);
return dataRead;
}
void rtl8225z2_rf_init(struct net_device *dev)
{
struct r8180_priv *priv = ieee80211_priv(dev);
int i;
short channel = 1;
u16 brsr;
u32 data,addr;
priv->chan = channel;
rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
if(priv->card_type == USB)
rtl8225_host_usb_init(dev);
else
rtl8225_host_pci_init(dev);
write_nic_dword(dev, RF_TIMING, 0x000a8008);
brsr = read_nic_word(dev, BRSR);
write_nic_word(dev, BRSR, 0xffff);
write_nic_dword(dev, RF_PARA, 0x100044);
#if 1 //0->1
rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
write_nic_byte(dev, CONFIG3, 0x44);
rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
#endif
rtl8185_rf_pins_enable(dev);
// mdelay(1000);
write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
write_rtl8225(dev, 0x3, 0x441); mdelay(1);
write_rtl8225(dev, 0x4, 0x8c3);mdelay(1);
write_rtl8225(dev, 0x5, 0xc72);mdelay(1);
// }
write_rtl8225(dev, 0x6, 0xe6); mdelay(1);
write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel])); mdelay(1);
write_rtl8225(dev, 0x8, 0x3f); mdelay(1);
write_rtl8225(dev, 0x9, 0x335); mdelay(1);
write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
write_rtl8225(dev, 0xc, 0x850); mdelay(1);
write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
write_rtl8225(dev, 0xe, 0x2b); mdelay(1);
write_rtl8225(dev, 0xf, 0x114);
mdelay(100);
//if(priv->card_type != USB) /* maybe not needed even for 8185 */
// write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
write_rtl8225(dev, 0x0, 0x1b7);
for(i=0;i<95;i++){
write_rtl8225(dev, 0x1, (u8)(i+1));
#if 0
if(priv->phy_ver == 1)
/* version A */
write_rtl8225(dev, 0x2, rtl8225a_rxgain[i]);
else
#endif
/* version B & C & D*/
write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
}
write_rtl8225(dev, 0x3, 0x80);
write_rtl8225(dev, 0x5, 0x4);
write_rtl8225(dev, 0x0, 0xb7);
write_rtl8225(dev, 0x2, 0xc4d);
if(priv->card_type == USB){
// force_pci_posting(dev);
mdelay(200);
write_rtl8225(dev, 0x2, 0x44d);
// force_pci_posting(dev);
mdelay(100);
}//End of if(priv->card_type == USB)
/* FIXME!! rtl8187 we have to check if calibrarion
* is successful and eventually cal. again (repeat
* the two write on reg 2)
*/
// Check for calibration status, 2005.11.17,
data = read_rtl8225(dev, 6);
if (!(data&0x00000080))
{
write_rtl8225(dev, 0x02, 0x0c4d);
force_pci_posting(dev); mdelay(200);
write_rtl8225(dev, 0x02, 0x044d);
force_pci_posting(dev); mdelay(100);
data = read_rtl8225(dev, 6);
if (!(data&0x00000080))
{
DMESGW("RF Calibration Failed!!!!\n");
}
}
//force_pci_posting(dev);
mdelay(200); //200 for 8187
// //if(priv->card_type != USB){
// write_rtl8225(dev, 0x2, 0x44d);
// write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
// write_rtl8225(dev, 0x2, 0x47d);
//
// force_pci_posting(dev);
// mdelay(100);
//
// write_rtl8225(dev, 0x2, 0x44d);
// //}
write_rtl8225(dev, 0x0, 0x2bf);
if(priv->card_type != USB)
rtl8185_rf_pins_enable(dev);
//set up ZEBRA AGC table, 2005.11.17,
for(i=0;i<128;i++){
data = rtl8225_agc[i];
addr = i + 0x80; //enable writing AGC table
write_phy_ofdm(dev, 0xb, data);
mdelay(1);
write_phy_ofdm(dev, 0xa, addr);
mdelay(1);
}
#if 0
for(i=0;i<128;i++){
write_phy_ofdm(dev, 0xb, rtl8225_agc[i]);
mdelay(1);
write_phy_ofdm(dev, 0xa, (u8)i+ 0x80);
mdelay(1);
}
#endif
force_pci_posting(dev);
mdelay(1);
write_phy_ofdm(dev, 0x0, 0x1); mdelay(1);
write_phy_ofdm(dev, 0x1, 0x2); mdelay(1);
write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1);
write_phy_ofdm(dev, 0x3, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x4, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x5, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x6, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x7, 0x0); mdelay(1);
write_phy_ofdm(dev, 0x8, 0x40); mdelay(1);
write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1);
write_phy_ofdm(dev, 0xa, 0x8); mdelay(1);
//write_phy_ofdm(dev, 0x18, 0xef);
// }
//}
write_phy_ofdm(dev, 0xb, 0x80); mdelay(1);
write_phy_ofdm(dev, 0xc, 0x1);mdelay(1);
//if(priv->card_type != USB)
write_phy_ofdm(dev, 0xd, 0x43);
write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1);
#if 0
if(priv->card_8185 == 1){
if(priv->card_8185_Bversion)
write_phy_ofdm(dev, 0xf, 0x20);/*ver B*/
else
write_phy_ofdm(dev, 0xf, 0x28);/*ver C*/
}else{
#endif
write_phy_ofdm(dev, 0xf, 0x38);mdelay(1);
/*ver D & 8187*/
// }
// if(priv->card_8185 == 1 && priv->card_8185_Bversion)
// write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/
// else
write_phy_ofdm(dev, 0x10, 0x84);mdelay(1);
/*ver C & D & 8187*/
write_phy_ofdm(dev, 0x11, 0x07);mdelay(1);
/*agc resp time 700*/
// if(priv->card_8185 == 2){
/* Ver D & 8187*/
write_phy_ofdm(dev, 0x12, 0x20);mdelay(1);
write_phy_ofdm(dev, 0x13, 0x20);mdelay(1);
#if 0
}else{
u32 read_rtl8225(struct net_device *dev, u8 adr)
{
u32 data2Write = ((u32)(adr & 0x1f)) << 27;
u32 dataRead;
u32 mask;
u16 oval,oval2,oval3,tmp;
// ThreeWireReg twreg;
// ThreeWireReg tdata;
int i;
short bit, rw;
u8 wLength = 6;
u8 rLength = 12;
u8 low2high = 0;
oval = read_nic_word(dev, RFPinsOutput);
oval2 = read_nic_word(dev, RFPinsEnable);
oval3 = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsEnable, (oval2|0xf));
write_nic_word(dev, RFPinsSelect, (oval3|0xf));
dataRead = 0;
oval &= ~0xf;
write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
rw = 0;
mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
for(i = 0; i < wLength/2; i++)
{
bit = ((data2Write&mask) != 0) ? 1 : 0;
write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
mask = (low2high) ? (mask<<1): (mask>>1);
if(i == 2)
{
rw = BB_HOST_BANG_RW;
write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
break;
}
bit = ((data2Write&mask) != 0) ? 1: 0;
write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
mask = (low2high) ? (mask<<1) : (mask>>1);
}
//twreg.struc.clk = 0;
//twreg.struc.data = 0;
write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
for(i = 0; i < rLength; i++)
{
write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
tmp = read_nic_word(dev, RFPinsInput);
dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
mask = (low2high) ? (mask<<1) : (mask>>1);
}
write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
write_nic_word(dev, RFPinsEnable, oval2);
write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
write_nic_word(dev, RFPinsOutput, 0x3a0);
return dataRead;
}
void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
{
#ifdef THOMAS_3WIRE
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
int status;
data = (data << 4) | (u16)(adr & 0x0f);
//
// OUT a vendor request to ask 8051 do HW three write operation.
//
//printk("before write rtl8225 , data = %x\n",data);
status = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
0x04, RTL8187_REQT_WRITE,
0x0000, 0x1304, &data, 2, HZ / 2);
if (status < 0)
{
printk("write_rtl8225 TimeOut! status:%x\n", status);
}
/*mdelay(1);
u16 Tmpdata;
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
0x04, RTL8187_REQT_READ,
0x0000, 0x1304, &Tmpdata, 2, HZ / 2);
if (status < 0)
{
printk("read_rtl8225 TimeOut! status:%x\n", status);
}
printk("after read rtl8225 , data = %x\n",Tmpdata);*/
#else
#ifdef USE_8051_3WIRE
struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
struct usb_device *udev = priv->udev;
//u8 bit;
u16 wReg80, wReg82, wReg84;
wReg80 = read_nic_word(dev, RFPinsOutput);
wReg80 &= 0xfff3;
wReg82 = read_nic_word(dev, RFPinsEnable);
wReg84 = read_nic_word(dev, RFPinsSelect);
// <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
//wReg84 &= 0xfff0;
wReg84 &= 0xfff8; //modified by david according to windows segment code.
// We must set SW enabled before terminating HW 3-wire, 2005.07.29, by rcnjko.
write_nic_word(dev, RFPinsEnable, (wReg82|0x0007)); // Set To Output Enable
write_nic_word(dev, RFPinsSelect, (wReg84|0x0007)); // Set To SW Switch
force_pci_posting(dev);
udelay(10); //
write_nic_word(dev, 0x80, (BB_HOST_BANG_EN|wReg80)); // Set SI_EN (RFLE)
force_pci_posting(dev);
udelay(2);
//twreg.struc.enableB = 0;
write_nic_word(dev, 0x80, (wReg80)); // Clear SI_EN (RFLE)
force_pci_posting(dev);
udelay(10);
usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
RTL8187_REQ_SET_REGS, RTL8187_REQT_WRITE,
adr, 0x8225, &data, 2, HZ / 2);
write_nic_word(dev, 0x80, (BB_HOST_BANG_EN|wReg80));
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, 0x80, (wReg80|0x0004));
write_nic_word(dev, 0x84, (wReg84|0x0000));// Set To SW Switch
if(priv->card_type == USB)
mdelay(2);
else
rtl8185_rf_pins_enable(dev);
#else
int i;
u16 out,select;
u8 bit;
u32 bangdata = (data << 4) | (adr & 0xf);
struct r8180_priv *priv = ieee80211_priv(dev);
out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
write_nic_word(dev,RFPinsEnable,
(read_nic_word(dev,RFPinsEnable) | 0x7));
select = read_nic_word(dev, RFPinsSelect);
write_nic_word(dev, RFPinsSelect, select | 0x7 |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN );//| 0x1fff);
force_pci_posting(dev);
udelay(2);
write_nic_word(dev, RFPinsOutput, out);
force_pci_posting(dev);
udelay(10);
for(i=15; i>=0;i--){
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
i--;
bit = (bangdata & (1<<i)) >> i;
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
write_nic_word(dev, RFPinsOutput, bit | out);
}
write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
force_pci_posting(dev);
udelay(10);
write_nic_word(dev, RFPinsOutput, out |
((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
write_nic_word(dev, RFPinsSelect, select |
((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
if(priv->card_type == USB)
mdelay(2);
else
rtl8185_rf_pins_enable(dev);
#endif
#endif /*THOMAS_3WIRE*/
}
bool FirmwareDownload92S(struct net_device *dev)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rtStatus = true;
u8 *pucMappedFile = NULL;
u32 ulFileLength;
u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE;
rt_firmware *pFirmware = priv->pFirmware;
u8 FwStatus = FW_STATUS_INIT;
PRT_8192S_FIRMWARE_HDR pFwHdr = NULL;
PRT_8192S_FIRMWARE_PRIV pFwPriv = NULL;
pFirmware->FWStatus = FW_STATUS_INIT;
/*
* Load the firmware from RTL8192SU/rtl8192sfw.bin if necessary
*/
if (pFirmware->szFwTmpBufferLen == 0) {
if (FirmwareRequest92S(dev, pFirmware) != true)
goto DownloadFirmware_Fail;
}
FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
while (FwStatus != FW_STATUS_READY) {
/* Image buffer redirection. */
switch (FwStatus) {
case FW_STATUS_LOAD_IMEM:
pucMappedFile = pFirmware->FwIMEM;
ulFileLength = pFirmware->FwIMEMLen;
break;
case FW_STATUS_LOAD_EMEM:
pucMappedFile = pFirmware->FwEMEM;
ulFileLength = pFirmware->FwEMEMLen;
break;
case FW_STATUS_LOAD_DMEM:
/* Partial update the content of private header */
pFwHdr = pFirmware->pFwHeader;
pFwPriv = (PRT_8192S_FIRMWARE_PRIV)&pFwHdr->FWPriv;
FirmwareHeaderPriveUpdate(dev, pFwPriv);
pucMappedFile = (u8 *)(pFirmware->pFwHeader) +
RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
ulFileLength = FwHdrSize -
RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
break;
default:
RT_TRACE(COMP_ERR, "Unexpected Download step!!\n");
goto DownloadFirmware_Fail;
break;
}
/* <2> Download image file */
rtStatus = FirmwareDownloadCode(dev,
pucMappedFile,
ulFileLength);
if(rtStatus != true)
goto DownloadFirmware_Fail;
/* <3> Check whether load FW process is ready */
rtStatus = FirmwareCheckReady(dev, FwStatus);
if(rtStatus != true)
goto DownloadFirmware_Fail;
FwStatus = FirmwareGetNextStatus(pFirmware->FWStatus);
}
RT_TRACE(COMP_FIRMWARE, "%s(): Firmware Download Success", __func__);
return rtStatus;
DownloadFirmware_Fail:
RT_TRACE(COMP_ERR, "%s(): failed with TCR-Status: %x\n",
__func__, read_nic_word(dev, TCR));
rtStatus = false;
return rtStatus;
}
bool FirmwareRequest92S(struct net_device *dev, rt_firmware *pFirmware)
{
struct r8192_priv *priv = ieee80211_priv(dev);
bool rtStatus = true;
const char *pFwImageFileName[1] = {"RTL8192SU/rtl8192sfw.bin"};
u8 *pucMappedFile = NULL;
u32 ulInitStep = 0;
u8 FwHdrSize = RT_8192S_FIRMWARE_HDR_SIZE;
PRT_8192S_FIRMWARE_HDR pFwHdr = NULL;
u32 file_length = 0;
int rc;
const struct firmware *fw_entry;
rc = request_firmware(&fw_entry,
pFwImageFileName[ulInitStep],
&priv->udev->dev);
if (rc < 0)
goto RequestFirmware_Fail;
if (fw_entry->size > sizeof(pFirmware->szFwTmpBuffer)) {
RT_TRACE(COMP_ERR, "%s(): image file too large"
"for container buffer", __func__);
release_firmware(fw_entry);
goto RequestFirmware_Fail;
}
memcpy(pFirmware->szFwTmpBuffer, fw_entry->data, fw_entry->size);
pFirmware->szFwTmpBufferLen = fw_entry->size;
release_firmware(fw_entry);
pucMappedFile = pFirmware->szFwTmpBuffer;
file_length = pFirmware->szFwTmpBufferLen;
/* Retrieve FW header. */
pFirmware->pFwHeader = (PRT_8192S_FIRMWARE_HDR) pucMappedFile;
pFwHdr = pFirmware->pFwHeader;
RT_TRACE(COMP_FIRMWARE, "%s(): signature: %x, version: %x, "
"size: %x, imemsize: %x, sram size: %x",
__func__, pFwHdr->Signature, pFwHdr->Version,
pFwHdr->DMEMSize, pFwHdr->IMG_IMEM_SIZE,
pFwHdr->IMG_SRAM_SIZE);
pFirmware->FirmwareVersion = byte(pFwHdr->Version , 0);
if ((pFwHdr->IMG_IMEM_SIZE == 0) ||
(pFwHdr->IMG_IMEM_SIZE > sizeof(pFirmware->FwIMEM))) {
RT_TRACE(COMP_ERR, "%s(): memory for data image is less than"
" IMEM requires", __func__);
goto RequestFirmware_Fail;
} else {
pucMappedFile += FwHdrSize;
/* Retrieve IMEM image. */
memcpy(pFirmware->FwIMEM, pucMappedFile, pFwHdr->IMG_IMEM_SIZE);
pFirmware->FwIMEMLen = pFwHdr->IMG_IMEM_SIZE;
}
if (pFwHdr->IMG_SRAM_SIZE > sizeof(pFirmware->FwEMEM)) {
RT_TRACE(COMP_ERR, "%s(): memory for data image is less than"
" EMEM requires", __func__);
goto RequestFirmware_Fail;
} else {
pucMappedFile += pFirmware->FwIMEMLen;
/* Retriecve EMEM image */
memcpy(pFirmware->FwEMEM, pucMappedFile, pFwHdr->IMG_SRAM_SIZE);
pFirmware->FwEMEMLen = pFwHdr->IMG_SRAM_SIZE;
}
return rtStatus;
RequestFirmware_Fail:
RT_TRACE(COMP_ERR, "%s(): failed with TCR-Status: %x\n",
__func__, read_nic_word(dev, TCR));
rtStatus = false;
return rtStatus;
}