uint8_t a2bus_swyft_device::read_c0nx(uint8_t offset) { switch (offset) { case 0: m_rombank = 0; m_inh_state = INH_READ; recalc_slot_inh(); break; case 1: m_rombank = 0; m_inh_state = INH_NONE; recalc_slot_inh(); break; case 2: m_rombank = 0x1000; m_inh_state = INH_READ; recalc_slot_inh(); break; } return 0xff; }
UINT8 a2bus_swyft_device::read_c0nx(address_space &space, UINT8 offset) { switch (offset) { case 0: m_rombank = 0; m_inh_state = INH_READ; recalc_slot_inh(); break; case 1: m_rombank = 0; m_inh_state = INH_NONE; recalc_slot_inh(); break; case 2: m_rombank = 0x1000; m_inh_state = INH_READ; recalc_slot_inh(); break; } return 0xff; }
void a2bus_swyft_device::device_reset() { m_rombank = 0; m_inh_state = INH_READ; // read-enable the ROM recalc_slot_inh(); }
void a2bus_swyft_device::write_c0nx(address_space &space, UINT8 offset, UINT8 data) { switch (offset) { case 0: m_rombank = 0; m_inh_state = INH_READ; recalc_slot_inh(); break; case 1: m_rombank = 0; m_inh_state = INH_NONE; recalc_slot_inh(); break; case 2: m_rombank = 0x1000; m_inh_state = INH_READ; recalc_slot_inh(); break; } }
void a2bus_swyft_device::write_c0nx(uint8_t offset, uint8_t data) { switch (offset) { case 0: m_rombank = 0; m_inh_state = INH_READ; recalc_slot_inh(); break; case 1: m_rombank = 0; m_inh_state = INH_NONE; recalc_slot_inh(); break; case 2: m_rombank = 0x1000; m_inh_state = INH_READ; recalc_slot_inh(); break; } }
void a2bus_ramcard_device::do_io(int offset) { int old_inh_state = m_inh_state; switch (offset) { case 0x1: case 0x3: case 0x9: case 0xb: if (offset != m_last_offset) { m_last_offset = offset; return; } break; } m_last_offset = offset; m_inh_state = INH_NONE; m_dxxx_bank = 0; if (offset & 0x1) { m_inh_state |= INH_WRITE; } switch(offset & 0x03) { case 0x00: case 0x03: m_inh_state |= INH_READ; break; } if (!(offset & 8)) { m_dxxx_bank = 0x1000; } if (m_inh_state != old_inh_state) { recalc_slot_inh(); } #if 0 printf("LC: new state %c%c dxxx=%04x\n", (m_inh_state & INH_READ) ? 'R' : 'x', (m_inh_state & INH_WRITE) ? 'W' : 'x', m_dxxx_bank); #endif }
void a2bus_ssramcard_device::do_io(int offset) { int old_inh_state = m_inh_state; switch (offset) { case 0x1: case 0x3: case 0x9: case 0xb: if (offset != m_last_offset) { m_last_offset = offset; return; } break; } m_last_offset = offset; if (offset & 4) { switch (offset) { case 0x4: m_main_bank = 0x00000; break; case 0x5: m_main_bank = 0x04000; break; case 0x6: m_main_bank = 0x08000; break; case 0x7: m_main_bank = 0x0c000; break; case 0xc: m_main_bank = 0x10000; break; case 0xd: m_main_bank = 0x14000; break; case 0xe: m_main_bank = 0x18000; break; case 0xf: m_main_bank = 0x1c000; break; } } else { m_inh_state = INH_NONE; m_dxxx_bank = 0; if (offset & 0x1) { m_inh_state |= INH_WRITE; } switch(offset & 0x03) { case 0x00: case 0x03: m_inh_state |= INH_READ; break; } if (!(offset & 8)) { m_dxxx_bank = 0x1000; } } if (m_inh_state != old_inh_state) { recalc_slot_inh(); } #if 0 printf("LC: (ofs %x) new state %c%c dxxx=%04x main=%05x\n", offset, (m_inh_state & INH_READ) ? 'R' : 'x', (m_inh_state & INH_WRITE) ? 'W' : 'x', m_dxxx_bank, m_main_bank); #endif }