//------------------------------------------------- // update_serial - //------------------------------------------------- void z80sio_channel::update_serial() { int data_bit_count = get_rx_word_length(); stop_bits_t stop_bits = get_stop_bits(); parity_t parity; LOG(("Z80SIO update_serial\n")); if (m_wr4 & WR4_PARITY_ENABLE) { if (m_wr4 & WR4_PARITY_EVEN) parity = PARITY_EVEN; else parity = PARITY_ODD; } else parity = PARITY_NONE; set_data_frame(1, data_bit_count, parity, stop_bits); int clocks = get_clock_mode(); if (m_rxc > 0) { set_rcv_rate(m_rxc / clocks); } if (m_txc > 0) { set_tra_rate(m_txc / clocks); } receive_register_reset(); // if stop bits is changed from 0, receive register has to be reset }
void i8251_device::device_reset() { LOG(("I8251: Reset\n")); /* what is the default setup when the 8251 has been reset??? */ /* i8251 datasheet explains the state of tx pin at reset */ /* tx is set to 1 */ set_out_data_bit(1); /* assumption, rts is set to 1 */ m_connection_state &= ~SERIAL_STATE_RTS; serial_connection_out(); transmit_register_reset(); receive_register_reset(); /* expecting mode byte */ m_flags |= I8251_EXPECTING_MODE; /* not expecting a sync byte */ m_flags &= ~I8251_EXPECTING_SYNC_BYTE; /* no character to read by cpu */ /* transmitter is ready and is empty */ m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY; m_mode_byte = 0; m_command = 0; /* update tx empty pin output */ update_tx_empty(); /* update rx ready pin output */ update_rx_ready(); /* update tx ready pin output */ update_tx_ready(); }
void lk201_device::device_reset() { m_beeper->adjust(attotime::never); m_speaker->set_state(0); m_speaker->set_output_gain(0, 0); ddrs[0] = ddrs[1] = ddrs[2] = 0; ports[0] = ports[1] = ports[2] = 0; set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1); set_rate(4800); m_count->adjust(attotime::from_hz(1200), 0, attotime::from_hz(1200)); memset(m_timer.regs, 0, sizeof(m_timer.regs)); sci_status = (SCSR_TC | SCSR_TDRE); spi_status = 0; spi_data = 0; kbd_data = 0; led_data = 0; transmit_register_reset(); receive_register_reset(); }
//------------------------------------------------- // reset - reset channel status //------------------------------------------------- void z80sio_channel::device_reset() { LOG("%s\n", FUNCNAME); // Reset RS232 emulation receive_register_reset(); transmit_register_reset(); // disable receiver m_wr3 &= ~WR3_RX_ENABLE; // disable transmitter m_wr5 &= ~WR5_TX_ENABLE; m_rr0 |= RR0_TX_BUFFER_EMPTY; m_rr1 |= RR1_ALL_SENT; // reset external lines set_rts(1); set_dtr(1); // reset interrupts if (m_index == z80sio_device::CHANNEL_A) { m_uart->reset_interrupts(); } }
void z80dart_channel::update_serial() { int data_bit_count = get_rx_word_length(); stop_bits_t stop_bits = get_stop_bits(); parity_t parity; if (m_wr[4] & WR4_PARITY_ENABLE) { if (m_wr[4] & WR4_PARITY_EVEN) parity = PARITY_EVEN; else parity = PARITY_ODD; } else parity = PARITY_NONE; set_data_frame(1, data_bit_count, parity, stop_bits); int clocks = get_clock_mode(); if (m_rxc > 0) { set_rcv_rate(m_rxc / clocks); } if (m_txc > 0) { set_tra_rate(m_txc / clocks); } receive_register_reset(); // if stop bits is changed from 0, receive register has to be reset (FIXME: doing this without checking is stupid) }
void wangpc_keyboard_device::device_reset() { receive_register_reset(); transmit_register_reset(); m_txd_handler(1); }
void octopus_keyboard_device::device_reset() { buffered_rs232_device::device_reset(); set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1); set_rcv_rate(1200); set_tra_rate(9600); receive_register_reset(); transmit_register_reset(); m_enabled = 0; m_delay = 500; // 3*100+200 m_repeat = 110; // 4^2*5+30 stop_processing(); reset_key_state(); typematic_stop(); clear_fifo(); output_dcd(0); output_dsr(0); output_cts(0); output_rxd(1); start_processing(attotime::from_hz(9600)); }
void wangpc_keyboard_device::device_reset() { transmit_register_reset(); receive_register_reset(); set_out_data_bit(1); serial_connection_out(); }
void z80sti_device::device_reset() { memset(m_tmc, 0, sizeof(m_tmc)); memset(m_to, 0, sizeof(m_to)); transmit_register_reset(); receive_register_reset(); }
void tms5501_device::device_reset() { receive_register_reset(); transmit_register_reset(); m_write_xmt(1); check_interrupt(); }
void ym3802_device::device_reset() { m_reg.clear(); reset_irq(0xff); transmit_register_reset(); receive_register_reset(); reset_midi_timer(); set_comms_mode(); }
void mos6551_device::device_reset() { m_ctrl = 0; m_cmd = CMD_RIE; transmit_register_reset(); receive_register_reset(); update_serial(); }
void graph_link_hle_device::device_reset() { set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1); set_rate(9600); receive_register_reset(); transmit_register_reset(); m_head = m_tail = 0; m_empty = true; m_ready = true; }
void apricot_keyboard_hle_device::device_reset() { clear_fifo(); receive_register_reset(); transmit_register_reset(); set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1); set_rcv_rate(7800); set_tra_rate(7800); reset_key_state(); start_processing(attotime::from_hz(7800)); }
void mc6852_device::device_reset() { m_rx_fifo = std::queue<UINT8>(); m_tx_fifo = std::queue<UINT8>(); receive_register_reset(); transmit_register_reset(); /* reset and inhibit receiver/transmitter sections */ m_cr[0] |= (C1_TX_RS | C1_RX_RS); m_cr[1] &= ~(C2_EIE | C2_PC2 | C2_PC1); m_status &= ~S_TDRA; /* set receiver shift register to all 1's */ m_rsr = 0xff; }
void im6402_device::device_reset() { transmit_register_reset(); receive_register_reset(); m_rrc_count = 0; m_trc_count = 0; m_rbr = 0; m_pe = 0; m_fe = 0; m_oe = 0; set_dr(CLEAR_LINE); set_tbre(ASSERT_LINE); set_tre(ASSERT_LINE); }
void m20_keyboard_device::device_reset() { buffered_rs232_device::device_reset(); reset_key_state(); clear_fifo(); set_data_frame(1, 8, PARITY_NONE, STOP_BITS_2); set_rate(1'200); receive_register_reset(); transmit_register_reset(); output_dcd(0); output_dsr(0); output_cts(0); output_rxd(1); start_processing(attotime::from_hz(1'200)); }
void z80dart_channel::device_reset() { receive_register_reset(); transmit_register_reset(); // disable receiver m_wr[3] &= ~WR3_RX_ENABLE; // disable transmitter m_wr[5] &= ~WR5_TX_ENABLE; m_rr[0] |= RR0_TX_BUFFER_EMPTY; // reset external lines set_rts(1); set_dtr(1); // reset interrupts if (m_index == z80dart_device::CHANNEL_A) { m_uart->reset_interrupts(); } }
void mc2661_device::device_reset() { receive_register_reset(); transmit_register_reset(); m_mr[0] = m_mr[1] = 0; m_sync[0] = m_sync[1] = m_sync[2] = 0; m_cr = 0; m_sr = 0; m_mode_index = 0; m_sync_index = 0; m_write_txd(1); m_write_rxrdy(CLEAR_LINE); m_write_txrdy(CLEAR_LINE); m_write_rts(1); m_write_dtr(1); m_write_txemt_dschg(CLEAR_LINE); m_write_bkdet(0); m_write_xsync(0); }
void i8251_device::device_reset() { LOG("I8251: Reset\n"); /* what is the default setup when the 8251 has been reset??? */ /* i8251 datasheet explains the state of tx pin at reset */ /* tx is set to 1 */ m_txd_handler(1); /* assumption */ m_rts_handler(1); m_dtr_handler(1); transmit_register_reset(); receive_register_reset(); m_flags = 0; /* expecting mode byte */ m_flags |= I8251_EXPECTING_MODE; /* not expecting a sync byte */ m_flags &= ~I8251_EXPECTING_SYNC_BYTE; /* no character to read by cpu */ /* transmitter is ready and is empty */ m_status = I8251_STATUS_TX_EMPTY | I8251_STATUS_TX_READY; m_mode_byte = 0; m_command = 0; m_rx_data = 0; m_tx_data = 0; m_rxc_count = m_txc_count = 0; m_br_factor = 1; /* update tx empty pin output */ update_tx_empty(); /* update rx ready pin output */ update_rx_ready(); /* update tx ready pin output */ update_tx_ready(); }
void x68k_keyboard_device::device_reset() { buffered_rs232_device::device_reset(); set_data_frame(1, 8, PARITY_NONE, STOP_BITS_1); set_rate(38'400); // TODO: Should be 2400 but MC68901 doesn't support divide by 16 receive_register_reset(); transmit_register_reset(); m_enabled = 0; m_delay = 500; // 3*100+200 m_repeat = 110; // 4^2*5+30 stop_processing(); reset_key_state(); typematic_stop(); clear_fifo(); output_dcd(0); output_dsr(0); output_cts(0); output_rxd(1); }
void mc68901_device::device_reset() { m_tsr = 0; m_transmit_pending = false; m_overrun_pending = false; // Avoid read-before-write m_ipr = m_imr = 0; m_next_rsr = 0; memset(m_tmc, 0, sizeof(m_tmc)); memset(m_ti, 0, sizeof(m_ti)); memset(m_to, 0, sizeof(m_to)); register_w(REGISTER_GPIP, 0); register_w(REGISTER_AER, 0); register_w(REGISTER_DDR, 0); register_w(REGISTER_IERA, 0); register_w(REGISTER_IERB, 0); register_w(REGISTER_IPRA, 0); register_w(REGISTER_IPRB, 0); register_w(REGISTER_ISRA, 0); register_w(REGISTER_ISRB, 0); register_w(REGISTER_IMRA, 0); register_w(REGISTER_IMRB, 0); register_w(REGISTER_VR, 0); register_w(REGISTER_TACR, 0); register_w(REGISTER_TBCR, 0); register_w(REGISTER_TCDCR, 0); register_w(REGISTER_SCR, 0); register_w(REGISTER_UCR, 0); register_w(REGISTER_RSR, 0); transmit_register_reset(); receive_register_reset(); }
//------------------------------------------------- // update_serial - //------------------------------------------------- void z80sio_channel::update_serial() { int data_bit_count = get_rx_word_length(); stop_bits_t stop_bits = get_stop_bits(); parity_t parity; LOG("%s\n", FUNCNAME); if (m_wr4 & WR4_PARITY_ENABLE) { LOG("- Parity enabled\n"); if (m_wr4 & WR4_PARITY_EVEN) parity = PARITY_EVEN; else parity = PARITY_ODD; } else parity = PARITY_NONE; set_data_frame(1, data_bit_count, parity, stop_bits); int clocks = get_clock_mode(); if (m_rxc > 0) { LOG("- RxC:%d/%d = %d\n", m_rxc, clocks, m_rxc / clocks); set_rcv_rate(m_rxc / clocks); } if (m_txc > 0) { LOG("- TxC:%d/%d = %d\n", m_txc, clocks, m_txc / clocks); set_tra_rate(m_txc / clocks); } receive_register_reset(); // if stop bits is changed from 0, receive register has to be reset }
void mc68901_device::register_w(offs_t offset, uint8_t data) { switch (offset) { case REGISTER_GPIP: LOG("MC68901 General Purpose I/O : %x\n", data); m_gpip = data; gpio_output(); break; case REGISTER_AER: LOG("MC68901 Active Edge Register : %x\n", data); m_aer = data; break; case REGISTER_DDR: LOG("MC68901 Data Direction Register : %x\n", data); m_ddr = data; gpio_output(); break; case REGISTER_IERA: LOG("MC68901 Interrupt Enable Register A : %x\n", data); m_ier = (data << 8) | (m_ier & 0xff); m_ipr &= m_ier; check_interrupts(); break; case REGISTER_IERB: LOG("MC68901 Interrupt Enable Register B : %x\n", data); m_ier = (m_ier & 0xff00) | data; m_ipr &= m_ier; check_interrupts(); break; case REGISTER_IPRA: LOG("MC68901 Interrupt Pending Register A : %x\n", data); m_ipr &= (data << 8) | (m_ipr & 0xff); check_interrupts(); break; case REGISTER_IPRB: LOG("MC68901 Interrupt Pending Register B : %x\n", data); m_ipr &= (m_ipr & 0xff00) | data; check_interrupts(); break; case REGISTER_ISRA: LOG("MC68901 Interrupt In-Service Register A : %x\n", data); m_isr &= (data << 8) | (m_isr & 0xff); break; case REGISTER_ISRB: LOG("MC68901 Interrupt In-Service Register B : %x\n", data); m_isr &= (m_isr & 0xff00) | data; break; case REGISTER_IMRA: LOG("MC68901 Interrupt Mask Register A : %x\n", data); m_imr = (data << 8) | (m_imr & 0xff); m_isr &= m_imr; check_interrupts(); break; case REGISTER_IMRB: LOG("MC68901 Interrupt Mask Register B : %x\n", data); m_imr = (m_imr & 0xff00) | data; m_isr &= m_imr; check_interrupts(); break; case REGISTER_VR: LOG("MC68901 Interrupt Vector : %x\n", data & 0xf0); m_vr = data & 0xf8; if (m_vr & VR_S) { LOG("MC68901 Software End-Of-Interrupt Mode\n"); } else { LOG("MC68901 Automatic End-Of-Interrupt Mode\n"); m_isr = 0; } break; case REGISTER_TACR: m_tacr = data & 0x1f; switch (m_tacr & 0x0f) { case TCR_TIMER_STOPPED: LOG("MC68901 Timer A Stopped\n"); m_timer[TIMER_A]->enable(false); break; case TCR_TIMER_DELAY_4: case TCR_TIMER_DELAY_10: case TCR_TIMER_DELAY_16: case TCR_TIMER_DELAY_50: case TCR_TIMER_DELAY_64: case TCR_TIMER_DELAY_100: case TCR_TIMER_DELAY_200: { int divisor = PRESCALER[m_tacr & 0x07]; LOG("MC68901 Timer A Delay Mode : %u Prescale\n", divisor); m_timer[TIMER_A]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor)); } break; case TCR_TIMER_EVENT: LOG("MC68901 Timer A Event Count Mode\n"); m_timer[TIMER_A]->enable(false); break; case TCR_TIMER_PULSE_4: case TCR_TIMER_PULSE_10: case TCR_TIMER_PULSE_16: case TCR_TIMER_PULSE_50: case TCR_TIMER_PULSE_64: case TCR_TIMER_PULSE_100: case TCR_TIMER_PULSE_200: { int divisor = PRESCALER[m_tacr & 0x07]; LOG("MC68901 Timer A Pulse Width Mode : %u Prescale\n", divisor); m_timer[TIMER_A]->adjust(attotime::never, 0, attotime::from_hz(m_timer_clock / divisor)); m_timer[TIMER_A]->enable(false); } break; } if (m_tacr & TCR_TIMER_RESET) { LOG("MC68901 Timer A Reset\n"); m_to[TIMER_A] = 0; m_out_tao_cb(m_to[TIMER_A]); } break; case REGISTER_TBCR: m_tbcr = data & 0x1f; switch (m_tbcr & 0x0f) { case TCR_TIMER_STOPPED: LOG("MC68901 Timer B Stopped\n"); m_timer[TIMER_B]->enable(false); break; case TCR_TIMER_DELAY_4: case TCR_TIMER_DELAY_10: case TCR_TIMER_DELAY_16: case TCR_TIMER_DELAY_50: case TCR_TIMER_DELAY_64: case TCR_TIMER_DELAY_100: case TCR_TIMER_DELAY_200: { int divisor = PRESCALER[m_tbcr & 0x07]; LOG("MC68901 Timer B Delay Mode : %u Prescale\n", divisor); m_timer[TIMER_B]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor)); } break; case TCR_TIMER_EVENT: LOG("MC68901 Timer B Event Count Mode\n"); m_timer[TIMER_B]->enable(false); break; case TCR_TIMER_PULSE_4: case TCR_TIMER_PULSE_10: case TCR_TIMER_PULSE_16: case TCR_TIMER_PULSE_50: case TCR_TIMER_PULSE_64: case TCR_TIMER_PULSE_100: case TCR_TIMER_PULSE_200: { int divisor = PRESCALER[m_tbcr & 0x07]; LOG("MC68901 Timer B Pulse Width Mode : %u Prescale\n", DIVISOR); m_timer[TIMER_B]->adjust(attotime::never, 0, attotime::from_hz(m_timer_clock / divisor)); m_timer[TIMER_B]->enable(false); } break; } if (m_tacr & TCR_TIMER_RESET) { LOG("MC68901 Timer B Reset\n"); m_to[TIMER_B] = 0; m_out_tbo_cb(m_to[TIMER_B]); } break; case REGISTER_TCDCR: m_tcdcr = data & 0x77; switch (m_tcdcr & 0x07) { case TCR_TIMER_STOPPED: LOG("MC68901 Timer D Stopped\n"); m_timer[TIMER_D]->enable(false); break; case TCR_TIMER_DELAY_4: case TCR_TIMER_DELAY_10: case TCR_TIMER_DELAY_16: case TCR_TIMER_DELAY_50: case TCR_TIMER_DELAY_64: case TCR_TIMER_DELAY_100: case TCR_TIMER_DELAY_200: { int divisor = PRESCALER[m_tcdcr & 0x07]; LOG("MC68901 Timer D Delay Mode : %u Prescale\n", divisor); m_timer[TIMER_D]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor)); } break; } switch ((m_tcdcr >> 4) & 0x07) { case TCR_TIMER_STOPPED: LOG("MC68901 Timer C Stopped\n"); m_timer[TIMER_C]->enable(false); break; case TCR_TIMER_DELAY_4: case TCR_TIMER_DELAY_10: case TCR_TIMER_DELAY_16: case TCR_TIMER_DELAY_50: case TCR_TIMER_DELAY_64: case TCR_TIMER_DELAY_100: case TCR_TIMER_DELAY_200: { int divisor = PRESCALER[(m_tcdcr >> 4) & 0x07]; LOG("MC68901 Timer C Delay Mode : %u Prescale\n", divisor); m_timer[TIMER_C]->adjust(attotime::from_hz(m_timer_clock / divisor), 0, attotime::from_hz(m_timer_clock / divisor)); } break; } break; case REGISTER_TADR: LOG("MC68901 Timer A Data Register : %x\n", data); m_tdr[TIMER_A] = data; if (!m_timer[TIMER_A]->enabled()) { m_tmc[TIMER_A] = data; } break; case REGISTER_TBDR: LOG("MC68901 Timer B Data Register : %x\n", data); m_tdr[TIMER_B] = data; if (!m_timer[TIMER_B]->enabled()) { m_tmc[TIMER_B] = data; } break; case REGISTER_TCDR: LOG("MC68901 Timer C Data Register : %x\n", data); m_tdr[TIMER_C] = data; if (!m_timer[TIMER_C]->enabled()) { m_tmc[TIMER_C] = data; } break; case REGISTER_TDDR: LOG("MC68901 Timer D Data Register : %x\n", data); m_tdr[TIMER_D] = data; if (!m_timer[TIMER_D]->enabled()) { m_tmc[TIMER_D] = data; } break; case REGISTER_SCR: LOG("MC68901 Sync Character : %x\n", data); m_scr = data; break; case REGISTER_UCR: { int data_bit_count; switch (data & 0x60) { case UCR_WORD_LENGTH_8: default: data_bit_count = 8; break; case UCR_WORD_LENGTH_7: data_bit_count = 7; break; case UCR_WORD_LENGTH_6: data_bit_count = 6; break; case UCR_WORD_LENGTH_5: data_bit_count = 5; break; } parity_t parity; if (data & UCR_PARITY_ENABLED) { if (data & UCR_PARITY_EVEN) { LOG("MC68901 Parity : Even\n"); parity = PARITY_EVEN; } else { LOG("MC68901 Parity : Odd\n"); parity = PARITY_ODD; } } else { LOG("MC68901 Parity : Disabled\n"); parity = PARITY_NONE; } LOG("MC68901 Word Length : %u bits\n", data_bit_count); int start_bits; stop_bits_t stop_bits; switch (data & 0x18) { case UCR_START_STOP_0_0: default: start_bits = 0; stop_bits = STOP_BITS_0; LOG("MC68901 Start Bits : 0, Stop Bits : 0, Format : synchronous\n"); break; case UCR_START_STOP_1_1: start_bits = 1; stop_bits = STOP_BITS_1; LOG("MC68901 Start Bits : 1, Stop Bits : 1, Format : asynchronous\n"); break; case UCR_START_STOP_1_15: start_bits = 1; stop_bits = STOP_BITS_1_5; LOG("MC68901 Start Bits : 1, Stop Bits : 1.5, Format : asynchronous\n"); break; case UCR_START_STOP_1_2: start_bits = 1; stop_bits = STOP_BITS_2; LOG("MC68901 Start Bits : 1, Stop Bits : 2, Format : asynchronous\n"); break; } if (data & UCR_CLOCK_DIVIDE_16) { LOG("MC68901 Rx/Tx Clock Divisor : 16\n"); } else { LOG("MC68901 Rx/Tx Clock Divisor : 1\n"); } set_data_frame(start_bits, data_bit_count, parity, stop_bits); receive_register_reset(); m_ucr = data; } break; case REGISTER_RSR: if ((data & RSR_RCV_ENABLE) == 0) { LOG("MC68901 Receiver Disabled\n"); m_rsr = 0; } else { LOG("MC68901 Receiver Enabled\n"); if (data & RSR_SYNC_STRIP_ENABLE) { LOG("MC68901 Sync Strip Enabled\n"); } else { LOG("MC68901 Sync Strip Disabled\n"); } if (data & RSR_FOUND_SEARCH) LOG("MC68901 Receiver Search Mode Enabled\n"); m_rsr = data & 0x0b; } break; case REGISTER_TSR: m_tsr = (m_tsr & (TSR_BUFFER_EMPTY | TSR_UNDERRUN_ERROR | TSR_END_OF_XMIT)) | (data & ~(TSR_BUFFER_EMPTY | TSR_UNDERRUN_ERROR | TSR_END_OF_XMIT)); if ((data & TSR_XMIT_ENABLE) == 0) { LOG("MC68901 Transmitter Disabled\n"); m_tsr &= ~TSR_UNDERRUN_ERROR; if (is_transmit_register_empty()) m_tsr |= TSR_END_OF_XMIT; } else { LOG("MC68901 Transmitter Enabled\n"); switch (data & 0x06) { case TSR_OUTPUT_HI_Z: LOG("MC68901 Transmitter Disabled Output State : Hi-Z\n"); break; case TSR_OUTPUT_LOW: LOG("MC68901 Transmitter Disabled Output State : 0\n"); break; case TSR_OUTPUT_HIGH: LOG("MC68901 Transmitter Disabled Output State : 1\n"); break; case TSR_OUTPUT_LOOP: LOG("MC68901 Transmitter Disabled Output State : Loop\n"); break; } if (data & TSR_BREAK) { LOG("MC68901 Transmitter Break Enabled\n"); } else { LOG("MC68901 Transmitter Break Disabled\n"); } if (data & TSR_AUTO_TURNAROUND) { LOG("MC68901 Transmitter Auto Turnaround Enabled\n"); } else { LOG("MC68901 Transmitter Auto Turnaround Disabled\n"); } m_tsr &= ~TSR_END_OF_XMIT; if (m_transmit_pending && is_transmit_register_empty()) { transmit_register_setup(m_transmit_buffer); m_transmit_pending = false; } if (!m_transmit_pending) m_tsr |= TSR_BUFFER_EMPTY; } break; case REGISTER_UDR: LOG("MC68901 UDR %x\n", data); m_transmit_buffer = data; m_transmit_pending = true; m_tsr &= ~TSR_BUFFER_EMPTY; if ((m_tsr & TSR_XMIT_ENABLE) && is_transmit_register_empty()) { transmit_register_setup(m_transmit_buffer); m_transmit_pending = false; m_tsr |= TSR_BUFFER_EMPTY; } break; } }
void px4_state::machine_reset() { m_artsr = ART_TXRDY | ART_TXEMPTY; receive_register_reset(); transmit_register_reset(); }