void __init sci_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
#if !defined (CONFIG_HAVE_ARM_ARCH_TIMER)
int i = 0, ret = 0;
local_timer_register(&sprd_local_timer_ops);
for (i = 0; i < CONFIG_NR_CPUS; i++) {
ret = request_irq(irq_nr[i], __gptimer_interrupt,
IRQF_TIMER | IRQF_NOBALANCING | IRQF_DISABLED
| IRQF_PERCPU, "local_timer", local_evt);
if (ret) {
printk(KERN_ERR "request local timer irq %d failed\n",
irq_nr[i]);
}
}
#endif
#endif
/* setup aon timer timer1 and syscnt as clocksource */
__gptimer_clocksource_init();
__syscnt_clocksource_init("syscnt", 1000);
/* setup timer1 of aon timer as clockevent. */
sprd_gptimer_clockevent_init(BC_IRQ, "bctimer", 32768);
register_persistent_clock(NULL, sprd_read_persistent_clock);
printk(KERN_INFO "sci_timer_init\n");
}
static void __init tegra_init_rtc(struct device_node *np)
{
struct clk *clk;
#if defined(CONFIG_TEGRA_LP0_IN_IDLE)
int ret = 0;
#endif
/*
* rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled
*/
rtc_base = of_iomap(np, 0);
if (!rtc_base) {
pr_err("%s: Can't map RTC registers", __func__);
BUG();
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
clk = clk_get_sys("rtc-tegra", NULL);
#if defined(CONFIG_TEGRA_LP0_IN_IDLE)
/* clear out the hardware. */
writel(0, rtc_base + TEGRA_RTC_REG_MSEC_CDN_ALARM0);
writel(0xffffffff, rtc_base + TEGRA_RTC_REG_INTR_STATUS);
writel(0, rtc_base + TEGRA_RTC_REG_INTR_MASK);
ret = setup_irq(tegra_rtc_irq.irq, &tegra_rtc_irq);
if (ret) {
pr_err("Failed to register RTC IRQ: %d\n", ret);
BUG();
}
enable_irq_wake(tegra_rtc_irq.irq);
#endif
of_node_put(np);
if (IS_ERR(clk))
pr_warn("Unable to get rtc-tegra clock\n");
else
clk_prepare_enable(clk);
register_persistent_clock(NULL, tegra_read_persistent_clock);
}
static void __init tegra20_init_rtc(struct device_node *np)
{
struct clk *clk;
rtc_base = of_iomap(np, 0);
if (!rtc_base) {
pr_err("Can't map RTC registers");
BUG();
}
/*
* rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled
*/
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
pr_warn("Unable to get rtc-tegra clock\n");
else
clk_prepare_enable(clk);
register_persistent_clock(NULL, tegra_read_persistent_clock);
}
/**
* omap_init_clocksource_32k - setup and register counter 32k as a
* kernel clocksource
* @pbase: base addr of counter_32k module
* @size: size of counter_32k to map
*
* Returns 0 upon success or negative error code upon failure.
*
*/
int __init omap_init_clocksource_32k(void __iomem *vbase)
{
int ret;
/*
* 32k sync Counter IP register offsets vary between the
* highlander version and the legacy ones.
* The 'SCHEME' bits(30-31) of the revision register is used
* to identify the version.
*/
if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
OMAP2_32KSYNCNT_REV_SCHEME)
sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
else
sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
/*
* 120000 rough estimate from the calculations in
* __clocksource_updatefreq_scale.
*/
clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
32768, NSEC_PER_SEC, 120000);
ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
250, 32, clocksource_mmio_readl_up);
if (ret) {
pr_err("32k_counter: can't register clocksource\n");
return ret;
}
setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
register_persistent_clock(NULL, omap_read_persistent_clock);
pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
return 0;
}
static int __devinit exynos_persistent_clock_probe(struct platform_device *pdev)
{
struct resource *res;
struct rtc_time tm;
unsigned int tmp;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENOENT;
exynos_rtc_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(exynos_rtc_base))
return PTR_ERR(exynos_rtc_base);
rtc_clk = devm_clk_get(&pdev->dev, "gate_rtc");
if (IS_ERR(rtc_clk)) {
int ret;
dev_err(&pdev->dev, "failed to find rtc clock source\n");
ret = PTR_ERR(rtc_clk);
rtc_clk = NULL;
return ret;
}
clk_prepare_enable(rtc_clk);
/*
* initializing rtc with valid time values because of
* undefined reset values
*/
tm.tm_year = 100;
tm.tm_mon = 1;
tm.tm_mday = 1;
tm.tm_hour = 0;
tm.tm_min = 0;
tm.tm_sec = 0;
/* enable rtc before writing bcd values */
tmp = readw(exynos_rtc_base + S3C2410_RTCCON);
writew(tmp | S3C2410_RTCCON_RTCEN,
exynos_rtc_base + S3C2410_RTCCON);
tmp = readw(exynos_rtc_base + S3C2410_RTCCON);
writew(tmp & ~S3C2410_RTCCON_CNTSEL,
exynos_rtc_base + S3C2410_RTCCON);
tmp = readw(exynos_rtc_base + S3C2410_RTCCON);
writew(tmp & ~S3C2410_RTCCON_CLKRST,
exynos_rtc_base + S3C2410_RTCCON);
writeb(bin2bcd(tm.tm_sec), exynos_rtc_base + S3C2410_RTCSEC);
writeb(bin2bcd(tm.tm_min), exynos_rtc_base + S3C2410_RTCMIN);
writeb(bin2bcd(tm.tm_hour), exynos_rtc_base + S3C2410_RTCHOUR);
writeb(bin2bcd(tm.tm_mday), exynos_rtc_base + S3C2410_RTCDATE);
writeb(bin2bcd(tm.tm_mon), exynos_rtc_base + S3C2410_RTCMON);
writeb(bin2bcd(tm.tm_year - 100), exynos_rtc_base + S3C2410_RTCYEAR);
pr_debug("%s: set time %04d.%02d.%02d %02d:%02d:%02d\n", __func__,
1900 + tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour,
tm.tm_min, tm.tm_sec);
/* checking rtc time values are valid or not */
exynos_persistent_clock_read(&tm);
BUG_ON(rtc_valid_tm(&tm)) ;
tmp = readw(exynos_rtc_base + S3C2410_RTCCON);
tmp &= ~S3C2410_RTCCON_RTCEN;
writew(tmp, exynos_rtc_base + S3C2410_RTCCON);
clk_disable(rtc_clk);
register_persistent_clock(NULL, exynos_read_persistent_clock);
return 0;
}
static void __init tegra20_init_timer(void)
{
struct device_node *np;
struct clk *clk;
unsigned long rate;
int ret;
np = of_find_matching_node(NULL, timer_match);
if (!np) {
pr_err("Failed to find timer DT node\n");
BUG();
}
timer_reg_base = of_iomap(np, 0);
if (!timer_reg_base) {
pr_err("Can't map timer registers\n");
BUG();
}
tegra_timer_irq.irq = irq_of_parse_and_map(np, 2);
if (tegra_timer_irq.irq <= 0) {
pr_err("Failed to map timer IRQ\n");
BUG();
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
}
of_node_put(np);
np = of_find_matching_node(NULL, rtc_match);
if (!np) {
pr_err("Failed to find RTC DT node\n");
BUG();
}
rtc_base = of_iomap(np, 0);
if (!rtc_base) {
pr_err("Can't map RTC registers");
BUG();
}
/*
* rtc registers are used by read_persistent_clock, keep the rtc clock
* enabled
*/
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
pr_warn("Unable to get rtc-tegra clock\n");
else
clk_prepare_enable(clk);
of_node_put(np);
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
default:
WARN(1, "Unknown clock rate");
}
setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
pr_err("Failed to register clocksource\n");
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
pr_err("Failed to register timer IRQ: %d\n", ret);
BUG();
}
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_config_and_register(&tegra_clockevent, 1000000,
0x1, 0x1fffffff);
#ifdef CONFIG_HAVE_ARM_TWD
twd_local_timer_of_register();
#endif
register_persistent_clock(NULL, tegra_read_persistent_clock);
}
