static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); u32 mask = BIT(offset - bank->gpio_chip.base); dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n", offset, bank->gpio_chip.base, bank->id, mask); regmap_write_bits(pctl->regmap, (bank->id ? PINMUX_PRIMARY_SEL1 : PINMUX_PRIMARY_SEL0), mask, 0); regmap_write_bits(pctl->regmap, (bank->id ? PINMUX_SECONDARY_SEL1 : PINMUX_SECONDARY_SEL0), mask, 0); regmap_write_bits(pctl->regmap, (bank->id ? PINMUX_TERTIARY_SEL1 : PINMUX_TERTIARY_SEL0), mask, 0); return 0; }
static void tas5720_fault_check_work(struct work_struct *work) { struct tas5720_data *tas5720 = container_of(work, struct tas5720_data, fault_check_work.work); struct device *dev = tas5720->codec->dev; unsigned int curr_fault; int ret; ret = regmap_read(tas5720->regmap, TAS5720_FAULT_REG, &curr_fault); if (ret < 0) { dev_err(dev, "failed to read FAULT register: %d\n", ret); goto out; } /* Check/handle all errors except SAIF clock errors */ curr_fault &= TAS5720_OCE | TAS5720_DCE | TAS5720_OTE; /* * Only flag errors once for a given occurrence. This is needed as * the TAS5720 will take time clearing the fault condition internally * during which we don't want to bombard the system with the same * error message over and over. */ if ((curr_fault & TAS5720_OCE) && !(tas5720->last_fault & TAS5720_OCE)) dev_crit(dev, "experienced an over current hardware fault\n"); if ((curr_fault & TAS5720_DCE) && !(tas5720->last_fault & TAS5720_DCE)) dev_crit(dev, "experienced a DC detection fault\n"); if ((curr_fault & TAS5720_OTE) && !(tas5720->last_fault & TAS5720_OTE)) dev_crit(dev, "experienced an over temperature fault\n"); /* Store current fault value so we can detect any changes next time */ tas5720->last_fault = curr_fault; if (!curr_fault) goto out; /* * Periodically toggle SDZ (shutdown bit) H->L->H to clear any latching * faults as long as a fault condition persists. Always going through * the full sequence no matter the first return value to minimizes * chances for the device to end up in shutdown mode. */ ret = regmap_write_bits(tas5720->regmap, TAS5720_POWER_CTRL_REG, TAS5720_SDZ, 0); if (ret < 0) dev_err(dev, "failed to write POWER_CTRL register: %d\n", ret); ret = regmap_write_bits(tas5720->regmap, TAS5720_POWER_CTRL_REG, TAS5720_SDZ, TAS5720_SDZ); if (ret < 0) dev_err(dev, "failed to write POWER_CTRL register: %d\n", ret); out: /* Schedule the next fault check at the specified interval */ schedule_delayed_work(&tas5720->fault_check_work, msecs_to_jiffies(TAS5720_FAULT_CHECK_INTERVAL)); }
static int clk_utmi_enable(struct clk *clk) { struct clk *hw_parent; struct clk_utmi *utmi = to_clk_utmi(clk); unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN; unsigned int utmi_ref_clk_freq; unsigned long parent_rate; /* * If mainck rate is different from 12 MHz, we have to configure the * FREQ field of the SFR_UTMICKTRIM register to generate properly * the utmi clock. */ hw_parent = clk_get_parent(clk); parent_rate = clk_get_rate(hw_parent); switch (parent_rate) { case 12000000: utmi_ref_clk_freq = 0; break; case 16000000: utmi_ref_clk_freq = 1; break; case 24000000: utmi_ref_clk_freq = 2; break; /* * Not supported on SAMA5D2 but it's not an issue since MAINCK * maximum value is 24 MHz. */ case 48000000: utmi_ref_clk_freq = 3; break; default: pr_err("UTMICK: unsupported mainck rate\n"); return -EINVAL; } if (utmi->regmap_sfr) { regmap_write_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM, AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq); } else if (utmi_ref_clk_freq) { pr_err("UTMICK: sfr node required\n"); return -EINVAL; } regmap_write_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr); while (!clk_utmi_ready(utmi->regmap_pmc)) barrier(); return 0; }
static void uniphier_tm_disable_sensor(struct uniphier_tm_dev *tdev) { struct regmap *map = tdev->regmap; /* disable alert interrupt */ regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL, PMALERTINTCTL_MASK, 0); /* stop PVT */ regmap_write_bits(map, tdev->data->block_base + PVTCTLEN, PVTCTLEN_EN, 0); usleep_range(1000, 2000); /* The spec note says at least 1ms */ }
static int uniphier_tm_initialize_sensor(struct uniphier_tm_dev *tdev) { struct regmap *map = tdev->regmap; u32 val; u32 tmod_calib[2]; int ret; /* stop PVT */ regmap_write_bits(map, tdev->data->block_base + PVTCTLEN, PVTCTLEN_EN, 0); /* * Since SoC has a calibrated value that was set in advance, * TMODCOEF shows non-zero and PVT refers the value internally. * * If TMODCOEF shows zero, the boards don't have the calibrated * value, and the driver has to set default value from DT. */ ret = regmap_read(map, tdev->data->map_base + TMODCOEF, &val); if (ret) return ret; if (!val) { /* look for the default values in DT */ ret = of_property_read_u32_array(tdev->dev->of_node, "socionext,tmod-calibration", tmod_calib, ARRAY_SIZE(tmod_calib)); if (ret) return ret; regmap_write(map, tdev->data->tmod_setup_addr, TMODSETUP0_EN | TMODSETUP0_VAL(tmod_calib[0]) | TMODSETUP1_EN | TMODSETUP1_VAL(tmod_calib[1])); } /* select temperature mode */ regmap_write_bits(map, tdev->data->block_base + PVTCTLMODE, PVTCTLMODE_MASK, PVTCTLMODE_TEMPMON); /* set monitoring period */ regmap_write_bits(map, tdev->data->block_base + EMONREPEAT, EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD, EMONREPEAT_ENDLESS | EMONREPEAT_PERIOD_1000000); /* set monitor mode */ regmap_write_bits(map, tdev->data->map_base + PVTCTLSEL, PVTCTLSEL_MASK, PVTCTLSEL_MONITOR); return 0; }
static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev, unsigned int func, unsigned int group) { struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); const struct oxnas_pin_group *pg = &pctl->groups[group]; const struct oxnas_function *pf = &pctl->functions[func]; const char *fname = pf->name; struct oxnas_desc_function *functions = pg->functions; u32 mask = BIT(pg->pin); while (functions->name) { if (!strcmp(functions->name, fname)) { dev_dbg(pctl->dev, "setting function %s bank %d pin %d fct %d mask %x\n", fname, pg->bank, pg->pin, functions->fct, mask); regmap_write_bits(pctl->regmap, (pg->bank ? PINMUX_PRIMARY_SEL1 : PINMUX_PRIMARY_SEL0), mask, (functions->fct == 1 ? mask : 0)); regmap_write_bits(pctl->regmap, (pg->bank ? PINMUX_SECONDARY_SEL1 : PINMUX_SECONDARY_SEL0), mask, (functions->fct == 2 ? mask : 0)); regmap_write_bits(pctl->regmap, (pg->bank ? PINMUX_TERTIARY_SEL1 : PINMUX_TERTIARY_SEL0), mask, (functions->fct == 3 ? mask : 0)); return 0; } functions++; } dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func); return -EINVAL; }
static int da8xx_usb0_clk48_enable(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int mask, val; int ret; /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled * temporaily. It can be turned back off once the PLL is locked. */ clk_enable(usb0->fck); /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1 * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used. */ mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON; val = CFGCHIP2_PHY_PLLON; regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val, val & CFGCHIP2_PHYCLKGD, 0, 500000); clk_disable(usb0->fck); return ret; }
static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index) { struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw); unsigned int val = index ? clk->mask : 0; return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val); }
static int uniphier_clk_gate_endisable(struct clk_hw *hw, int enable) { struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw); return regmap_write_bits(gate->regmap, gate->reg, BIT(gate->bit), enable ? BIT(gate->bit) : 0); }
static int uniphier_reset_update(struct reset_controller_dev *rcdev, unsigned long id, int assert) { struct uniphier_reset_priv *priv = to_uniphier_reset_priv(rcdev); const struct uniphier_reset_data *p; for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { unsigned int mask, val; if (p->id != id) continue; mask = BIT(p->bit); if (assert) val = mask; else val = ~mask; if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) val = ~val; return regmap_write_bits(priv->regmap, p->reg, mask, val); } dev_err(priv->dev, "reset_id=%lu was not handled\n", id); return -EINVAL; }
static void clk_pll_disable(struct clk *clk) { struct clk_pll *pll = to_clk_pll(clk); unsigned int mask = pll->layout->pllr_mask; regmap_write_bits(pll->regmap, PLL_REG(pll->id), mask, ~mask); }
static int ks_sa_rng_init(struct hwrng *rng) { u32 value; struct device *dev = (struct device *)rng->priv; struct ks_sa_rng *ks_sa_rng = dev_get_drvdata(dev); /* Enable RNG module */ regmap_write_bits(ks_sa_rng->regmap_cfg, SA_CMD_STATUS_OFS, SA_CMD_STATUS_REG_TRNG_ENABLE, SA_CMD_STATUS_REG_TRNG_ENABLE); /* Configure RNG module */ writel(0, &ks_sa_rng->reg_rng->control); value = TRNG_DEF_STARTUP_CYCLES << TRNG_CNTL_REG_STARTUP_CYCLES_SHIFT; writel(value, &ks_sa_rng->reg_rng->control); value = (TRNG_DEF_MIN_REFILL_CYCLES << TRNG_CFG_REG_MIN_REFILL_CYCLES_SHIFT) | (TRNG_DEF_MAX_REFILL_CYCLES << TRNG_CFG_REG_MAX_REFILL_CYCLES_SHIFT) | (TRNG_DEF_CLK_DIV_CYCLES << TRNG_CFG_REG_SAMPLE_DIV_SHIFT); writel(value, &ks_sa_rng->reg_rng->config); /* Disable all interrupts from TRNG */ writel(0, &ks_sa_rng->reg_rng->intmask); /* Enable RNG */ value = readl(&ks_sa_rng->reg_rng->control); value |= TRNG_CNTL_REG_TRNG_ENABLE; writel(value, &ks_sa_rng->reg_rng->control); return 0; }
static void clk_utmi_disable(struct clk *clk) { struct clk_utmi *utmi = to_clk_utmi(clk); regmap_write_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0); }
static void da8xx_usb0_clk48_disable(struct clk_hw *hw) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int val; val = CFGCHIP2_PHYPWRDN; regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val); }
static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index) { struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw); return regmap_write_bits(usb1->regmap, CFGCHIP(2), CFGCHIP2_USB1PHYCLKMUX, index ? CFGCHIP2_USB1PHYCLKMUX : 0); }
static int da8xx_usb11_phy_power_off(struct phy *phy) { struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy); regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_USB1SUSPENDM, 0); clk_disable_unprepare(d_phy->usb11_clk); return 0; }
static void ks_sa_rng_cleanup(struct hwrng *rng) { struct device *dev = (struct device *)rng->priv; struct ks_sa_rng *ks_sa_rng = dev_get_drvdata(dev); /* Disable RNG */ writel(0, &ks_sa_rng->reg_rng->control); regmap_write_bits(ks_sa_rng->regmap_cfg, SA_CMD_STATUS_OFS, SA_CMD_STATUS_REG_TRNG_ENABLE, 0); }
static int clk_pll_enable(struct clk *clk) { struct clk_pll *pll = to_clk_pll(clk); struct regmap *regmap = pll->regmap; const struct clk_pll_layout *layout = pll->layout; const struct clk_pll_characteristics *characteristics = pll->characteristics; u8 id = pll->id; u32 mask = PLL_STATUS_MASK(id); int offset = PLL_REG(id); u8 out = 0; unsigned int pllr; unsigned int status; u8 div; u16 mul; regmap_read(regmap, offset, &pllr); div = PLL_DIV(pllr); mul = PLL_MUL(pllr, layout); regmap_read(regmap, AT91_PMC_SR, &status); if ((status & mask) && (div == pll->div && mul == pll->mul)) return 0; if (characteristics->out) out = characteristics->out[pll->range]; if (characteristics->icpll) regmap_write_bits(regmap, AT91_PMC_PLLICPR, PLL_ICPR_MASK(id), characteristics->icpll[pll->range] << PLL_ICPR_SHIFT(id)); regmap_write_bits(regmap, offset, layout->pllr_mask, pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) | (out << PLL_OUT_SHIFT) | ((pll->mul & layout->mul_mask) << layout->mul_shift)); while (!clk_pll_ready(regmap, pll->id)) barrier(); return 0; }
static void uniphier_tm_enable_sensor(struct uniphier_tm_dev *tdev) { struct regmap *map = tdev->regmap; int i; u32 bits = 0; for (i = 0; i < ALERT_CH_NUM; i++) if (tdev->alert_en[i]) bits |= PMALERTINTCTL_EN(i); /* enable alert interrupt */ regmap_write_bits(map, tdev->data->map_base + PMALERTINTCTL, PMALERTINTCTL_MASK, bits); /* start PVT */ regmap_write_bits(map, tdev->data->block_base + PVTCTLEN, PVTCTLEN_EN, PVTCTLEN_EN); usleep_range(700, 1500); /* The spec note says at least 700us */ }
static void uniphier_tm_set_alert(struct uniphier_tm_dev *tdev, u32 ch, u32 temp) { struct regmap *map = tdev->regmap; /* set alert temperature */ regmap_write_bits(map, tdev->data->map_base + SETALERT0 + (ch << 2), SETALERT_EN | SETALERT_TEMP_OVF, SETALERT_EN | SETALERT_TEMP_OVF_VALUE(temp / 1000)); }
static int da8xx_usb20_phy_power_off(struct phy *phy) { struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy); regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN, CFGCHIP2_OTGPWRDN); clk_disable_unprepare(d_phy->usb20_clk); return 0; }
static int da8xx_usb20_phy_power_on(struct phy *phy) { struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy); int ret; ret = clk_prepare_enable(d_phy->usb20_clk); if (ret) return ret; regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGPWRDN, 0); return 0; }
static void uniphier_tm_irq_clear(struct uniphier_tm_dev *tdev) { u32 mask = 0, bits = 0; int i; for (i = 0; i < ALERT_CH_NUM; i++) { mask |= (PMALERTINTCTL_CLR(i) | PMALERTINTCTL_SET(i)); bits |= PMALERTINTCTL_CLR(i); } /* clear alert interrupt */ regmap_write_bits(tdev->regmap, tdev->data->map_base + PMALERTINTCTL, mask, bits); }
static int uniphier_clk_cpugear_set_parent(struct clk_hw *hw, u8 index) { struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw); int ret; unsigned int val; ret = regmap_write_bits(gear->regmap, gear->regbase + UNIPHIER_CLK_CPUGEAR_SET, gear->mask, index); if (ret) return ret; ret = regmap_write_bits(gear->regmap, gear->regbase + UNIPHIER_CLK_CPUGEAR_SET, UNIPHIER_CLK_CPUGEAR_UPD_BIT, UNIPHIER_CLK_CPUGEAR_UPD_BIT); if (ret) return ret; return regmap_read_poll_timeout(gear->regmap, gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD, val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT), 0, 1); }
static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, bool enabled) { if (enabled) { u8 val; regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, SUN4I_TCON0_LVDS_IF_EN); /* * As their name suggest, these values only apply to the A31 * and later SoCs. We'll have to rework this when merging * support for the older SoCs. */ regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, SUN6I_TCON0_LVDS_ANA0_C(2) | SUN6I_TCON0_LVDS_ANA0_V(3) | SUN6I_TCON0_LVDS_ANA0_PD(2) | SUN6I_TCON0_LVDS_ANA0_EN_LDO); udelay(2); regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, SUN6I_TCON0_LVDS_ANA0_EN_MB, SUN6I_TCON0_LVDS_ANA0_EN_MB); udelay(2); regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, SUN6I_TCON0_LVDS_ANA0_EN_DRVC, SUN6I_TCON0_LVDS_ANA0_EN_DRVC); if (sun4i_tcon_get_pixel_depth(encoder) == 18) val = 7; else val = 0xf; regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); } else { regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, SUN4I_TCON0_LVDS_IF_EN, 0); } }
static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw); unsigned int mask, val; /* The parent clock rate must be one of the following */ mask = CFGCHIP2_REFFREQ_MASK; switch (parent_rate) { case 12000000: val = CFGCHIP2_REFFREQ_12MHZ; break; case 13000000: val = CFGCHIP2_REFFREQ_13MHZ; break; case 19200000: val = CFGCHIP2_REFFREQ_19_2MHZ; break; case 20000000: val = CFGCHIP2_REFFREQ_20MHZ; break; case 24000000: val = CFGCHIP2_REFFREQ_24MHZ; break; case 26000000: val = CFGCHIP2_REFFREQ_26MHZ; break; case 38400000: val = CFGCHIP2_REFFREQ_38_4MHZ; break; case 40000000: val = CFGCHIP2_REFFREQ_40MHZ; break; case 48000000: val = CFGCHIP2_REFFREQ_48MHZ; break; default: return 0; } regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val); /* USB 2.0 PLL always supplies 48MHz */ return 48000000; }
static int stm32_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *cpu_dai) { struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); unsigned long flags; int ret; spin_lock_irqsave(&i2s->irq_lock, flags); i2s->substream = substream; spin_unlock_irqrestore(&i2s->irq_lock, flags); ret = clk_prepare_enable(i2s->i2sclk); if (ret < 0) { dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); return ret; } return regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, I2S_IFCR_MASK, I2S_IFCR_MASK); }
/* * UniPhier Watchdog operations */ static int uniphier_watchdog_ping(struct watchdog_device *w) { struct uniphier_wdt_dev *wdev = watchdog_get_drvdata(w); unsigned int val; int ret; /* Clear counter */ ret = regmap_write_bits(wdev->regmap, WDTCTRL, WDTCTRL_CLEAR, WDTCTRL_CLEAR); if (!ret) /* * As SoC specification, after clear counter, * it needs to wait until counter status is 1. */ ret = regmap_read_poll_timeout(wdev->regmap, WDTCTRL, val, (val & WDTCTRL_STATUS), 0, WDTST_TIMEOUT); return ret; }
static irqreturn_t stm32_i2s_isr(int irq, void *devid) { struct stm32_i2s_data *i2s = (struct stm32_i2s_data *)devid; struct platform_device *pdev = i2s->pdev; u32 sr, ier; unsigned long flags; int err = 0; regmap_read(i2s->regmap, STM32_I2S_SR_REG, &sr); regmap_read(i2s->regmap, STM32_I2S_IER_REG, &ier); flags = sr & ier; if (!flags) { dev_dbg(&pdev->dev, "Spurious IRQ sr=0x%08x, ier=0x%08x\n", sr, ier); return IRQ_NONE; } regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG, I2S_IFCR_MASK, flags); if (flags & I2S_SR_OVR) { dev_dbg(&pdev->dev, "Overrun\n"); err = 1; } if (flags & I2S_SR_UDR) { dev_dbg(&pdev->dev, "Underrun\n"); err = 1; } if (flags & I2S_SR_TIFRE) dev_dbg(&pdev->dev, "Frame error\n"); spin_lock(&i2s->irq_lock); if (err && i2s->substream) snd_pcm_stop_xrun(i2s->substream); spin_unlock(&i2s->irq_lock); return IRQ_HANDLED; }
static int da8xx_usb20_phy_set_mode(struct phy *phy, enum phy_mode mode) { struct da8xx_usb_phy *d_phy = phy_get_drvdata(phy); u32 val; switch (mode) { case PHY_MODE_USB_HOST: /* Force VBUS valid, ID = 0 */ val = CFGCHIP2_OTGMODE_FORCE_HOST; break; case PHY_MODE_USB_DEVICE: /* Force VBUS valid, ID = 1 */ val = CFGCHIP2_OTGMODE_FORCE_DEVICE; break; case PHY_MODE_USB_OTG: /* Don't override the VBUS/ID comparators */ val = CFGCHIP2_OTGMODE_NO_OVERRIDE; break; default: return -EINVAL; } regmap_write_bits(d_phy->regmap, CFGCHIP(2), CFGCHIP2_OTGMODE_MASK, val); return 0; }