void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); report_bist_failure(bist); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been * replicated in every reference design since Parmer, so it is * believed to be required even though it is not documented in * the SoC BKDGs. Without this setting, there is no serial * output. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); hudson_lpc_decode(); outb(0x24, 0xCD6); outb(0x01, 0xCD7); *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ hudson_lpc_port80(); if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); post_code(0x40); AGESAWRAPPER(amdinitpost); }
void main(unsigned long bist) { /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { /* FIXME: Should be PC97307! */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); kbc1100_early_init(0x2e); kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); amd_initenv(); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); enable_pm(); enable_spd(); dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); disable_spd(); }
void main(unsigned long bist) { /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); smbus_fixup(&ctrl); /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); enable_mainboard_devices(); ddr_ram_setup(&ctrl); }
static void main(unsigned long bist) { device_t dev; /* Enable VGA; 32MB buffer. */ pci_write_config8(0, 0xe1, 0xdd); /* * Disable the firewire stuff, which apparently steps on IO 0+ on * reset. Doh! */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6305), 0); if (dev != PCI_DEV_INVALID) pci_write_config8(dev, 0x15, 0x1c); enable_vt8235_serial(); console_init(); enable_smbus(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // init_timer(); post_code(0x05); print_debug(" Enabling mainboard devices\n"); enable_mainboard_devices(); print_debug(" Enabling shadow ram\n"); enable_shadow_ram(); ddr_ram_setup((const struct mem_controller *)0); if (bist == 0) early_mtrr_init(); //dump_pci_devices(); }
void main(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); /* setup PCIe MMCONF base address */ pci_write_config32(PCI_DEV(0, 16, 0), 0x64, CONFIG_MMCONF_BASE_ADDRESS >> 16); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
void main(unsigned long bist) { int cbmem_was_initted; /* init_timer(); */ post_code(0x05); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); //print_pci_devices(); //dump_pci_devices(); cbmem_was_initted = !cbmem_recovery(0); timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); }
void * asmlinkage romstage_main(unsigned long bist) { int cbmem_was_initted; /* init_timer(); */ post_code(0x05); i82801ix_early_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); cbmem_was_initted = !cbmem_recovery(0); timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); /* Emulation uses fixed low stack during ramstage. */ return NULL; }
void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; u8 s3_resume; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); /* Set southbridge and Super I/O GPIOs. */ ich7_enable_lpc(); mb_lpc_setup(); console_init(); report_bist_failure(bist); enable_smbus(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); if (s3_resume) boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); quick_ram_check(); printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); }
void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); i5000_lpc_config(); winbond_enable_serial(SERIAL_DEV, 0x3f8); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); early_config(); setup_gpio(); enable_smbus(); outb(0x07, 0x11b8); /* These are smbus write captured with serialice. They seem to setup the clock generator */ smbus_write_byte(0x6f, 0x88, 0x1f); smbus_write_byte(0x6f, 0x81, 0xff); smbus_write_byte(0x6f, 0x82, 0xff); smbus_write_byte(0x6f, 0x80, 0x23); outb(0x03, 0x11b8); outb(0x01, 0x11b8); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1); i5000_fbdimm_init(); smbus_write_byte(0x69, 0x01, 0x01); }
static void main(unsigned long bist) { if (bist == 0) early_mtrr_init(); enable_vt8231_serial(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); vt8231_enable_rom(); enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); /* this is way more generic than we need. sdram_initialize(ARRAY_SIZE(cpu), cpu); */ sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); sdram_enable(0, (const struct mem_controller *) 0); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); #if IS_ENABLED(CONFIG_HUDSON_UART) configure_hudson_uart(); #endif post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); post_code(0x40); AGESAWRAPPER(amdinitpost); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val, wants_reset; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); } post_code(0x30); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); post_code(0x32); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. * It would be nice to fixup prink spinlocks for ROM XIP mode. * I think it could be done by putting the spinlock flag in the cache * of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); // Need to use TMICT to synconize FID/VID wants_reset = mcp55_early_setup_x(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } if (wants_reset) printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); //enable RTC pc87417_enable_dev(RTC_DEV); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_ms9185_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); //bx_a010- wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif #if 1 needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } #endif allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 int i; for(i=0;i<2;i++) { activate_spd_rom(sysinfo->ctrl+i); dump_smbus_registers(); } #endif #if 0 int i; for(i=1;i<256;i<<=1) { change_i2c_mux(i); dump_smbus_registers(); } #endif //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 print_pci_devices(); #endif #if 0 // dump_pci_devices(); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_khepri_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 dump_pci_devices(); #endif post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sb7xx_51xx_pci_port80(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); enable_rs780_dev8(); sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif rs780_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x40); // die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // die("After MCT init before CAR disabled."); rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); val = agesawrapper_amdinitmmio(); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = (void *)backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x42); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif /* Initialize i8259 pic */ post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x44); setup_i8254 (); post_code(0x50); copy_and_run(0); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sb600_lpc_port80(); /* sb600_pci_port80(); */ } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); enable_rs690_dev8(); sb600_lpc_init(); /* Pistachio used a FPGA to enable serial debug instead of a SIO * and it doesn't require any special setup. */ console_init(); post_code(0x03); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); setup_pistachio_resource_map(); setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); #endif wait_all_aps_started(bsp_apicid); /* it will set up chains and store link pair for optimization later, * it will init sblnk and sbbusn, nodes, sbdn */ ht_setup_chains_x(sysinfo); /* run _early_setup before soft-reset. */ rs690_early_setup(); sb600_early_setup(); post_code(0x04); /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } post_code(0x05); needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); post_code(0x06); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now; */ printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x07); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_code(0x08); rs690_before_pci_init(); sb600_before_pci_init(); post_cache_as_ram(); }
void main(unsigned long bist) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); if (bist == 0) enable_lapic(); /* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); udelay(200 * 1000); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); ich7_enable_lpc(); /* Set up the console */ console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); halt(); } /* Perform some early chipset initialization required * before RAM initialization can work */ i945_early_initialization(); s3resume = southbridge_detect_s3_resume(); /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(s3resume ? 2 : 0, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); /* Perform some initialization that must run before stage2 */ early_ich7_init(); /* This should probably go away. Until now it is required * and mainboard specific */ rcba_config(); /* Chipset Errata! */ fixup_i945_errata(); /* Initialize the internal PCIe links before we go into stage2 */ i945_late_initialization(s3resume); timestamp_add_now(TS_END_ROMSTAGE); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; val = agesawrapper_amdinitmmio(); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; pci_devfn_t dev; amd_initmmio(); /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); outb(0x24, 0xcd6); outb(0x1, 0xcd7); outb(0xea, 0xcd6); outb(0x1, 0xcd7); *(u8 *)0xfed80101 = 0x98; console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); #if 0 uint8_t tmp = 0; pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); /* Is serial flash enabled? Then enable writing to serial flash. */ if (tmp & 0x0e) { pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); pnp_set_logical_device(GPIO_DEV); /* Set Serial Flash interface to 0x0820 */ pnp_write_config(GPIO_DEV, 0x64, 0x08); pnp_write_config(GPIO_DEV, 0x65, 0x20); } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); #endif ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif init_timer(); // Need to use TMICT to synconize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); /* all ap stopped? */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init (CONFIG_SIO_PORT); /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ sio1036_early_init(0x4E); } post_code(0x31); uart_init(); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } post_code(0x32); val = agesawrapper_amdinitmmio(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } post_code(0x36); val = agesawrapper_amdinitearly (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); val = agesawrapper_amdinitpost (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x40); val = agesawrapper_amdinitenv (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); } /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x44); copy_and_run(0); post_code(0x45); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, 0, 0, 0, 0, // Node 1 DIMM1, DIMM3, 0, 0, 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); print_info("now booting... fallback\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); } // FIXME why is this executed again? ---> sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= k8t890_early_setup_ht(); if (needs_reset) { print_debug("ht reset -\n"); soft_reset(); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ enable_fid_change(); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }